VLSI Architecture for Speech Processing in Communications.
It is very much necessary to design a specific architecture to solve complex problems. Here the low cost VLSI architectures come under use to deal with these efforts. As we all the increase in the growth of usage for mobile phones worldwide, developing dedicated hardware on high volume products like these will benefit VLSI economically. Some VLSI approaches are economically feasible in architectural synthesis of DSP systems. In mobile phones speech processing plays a crucial role in solving complex DSP procedures as these involve, speech recognition, noise suppression, silence detection, pitch analysis and many more. FPGA is recommended for low price VLSI which is also widely used in the market. Here there is a specific architecture for suppressing surrounding noise in the mobile communication.
SPECTRAL SUBTRACTION METHODOLOGIES
For Speech Enhancement, Spectral Processing methods are simple and effective. Human speech perception is not sensitive to short-time phase this theory is exploited in these methods. In case of noisy speech pertaining to non-parametric model based methods, noise is estimated and removed from degraded using subtractive algorithms.
FIR DESIGN METHODOLOGIES
FIR filters crucially influence the operation and performance in noise estimation and thereby on the complete system. To process real time signals it is necessary to design filters with low power operation for a given throughput requirement. Efficient Filters can be designed using a MAC circuit that consumes less processing time and less hardware. Implementation of FIR in FPGA can be a simple MAC, Parallel or Semi-Parallel, and Multi-channel FIR.
PROPOSED METHODOLOGY
Multiplier circuits Based on Vedic mathematics performs faster than conventional Multiplier. Vedic multiplier describes Urdhra Trivagbhyam Algorithm from Ancient Vedic Mathematics. This methodology can be applied to any number of bits and takes any sign-bit extensions. In this algorithm partial products are obtained in between before arriving at the end result, hence multiplication of floating number of larger size is implemented using smaller size multiplication thus saving the computational time and reducing the complexity of the circuit.
