STA — Setup and Hold Time Analysis

Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. It helps to figure out the possible frequency in which the design could run without any timing violations.

fig 1

For the design output to be stable, it should meet setup and hold time. Any Input to the Flip-Flop in the design must be stable for small amount of time prior to the sampling clock edge. That small amount of time is called Setup Time. Also, the Input to the Flip-Flop must be stable for a minimum amount of time after the sampling clock edge. This time is called Hold Time.

fig 2

Consider two Flip-Flops as shown in the figure 2. The data is launched from clock cycle 1 of Launch FF and captured at clock cycle 2 of Capture FF. There is a combinational block introduced between the Launch Flip-Flop and Capture Flip-Flop. The time taken by combinational block is given as Tg. Also, there is a Buffer placed in the path of the clock of Capture FF which introduces delay between clock of Launch and Capture FF. This is generally referred as Clock Skew.

Setup Time Analysis at Capture FF:

1. Tcq1 is the time required for the data to propagate from Input to Launch FF Q1 at Launch Clock edge.
2. Tg is the time taken by the combinational block.
3. Tse2 is the setup time at Capture FF. This is the minimum time prior to the capture clock sampling edge before which the data has to be stable.
4. So, the Clock Period T of the design must be greater than or equal to Tcq1 + Tg + Tse2. Since, there is also Tskew introduced in the Capture Clock path,

Tcq1 + Tg + Tse2 <= T + Tskew

T >= Tcq1 + Tg + Tse2 — Tskew

5. Note: The Setup Time Analysis determines the minimum Clock Time Period T (Maximum Clock Frequency F) of the design.

6. Note: Tskew helps in avoiding setup time violation.

Hold Time Analysis at Setup FF:

1. The data launched at Clock cycle 1 of Launch FF is captured at Clock cycle 2 of Capture FF.
2. Since there is a clock skew between Launch and Capture FF, the data launched at Launch Clock cycle 2 may affect the data captured at Capture Clock cycle 2.
3. So, Tcq1 + Tg should be greater than Th(Hold time).
4. Due to the presence of clock skew,

Tcq1 + Tg >= Th + Tskew

Th <= (Tcq1 + Tg) — Tskew

5. Note: Tskew increases the chance of hold violation.