Watch Dog Timer Design
If a System hangs, there has to be some internal mechanism to reset the system automatically.This internal mechanism is implemented as Watch Dog Timer (WDT).
The Watch Dog Timer is a Hardware Timer which will be programmed in run time with a time interval. Within this Interval, the System is expected to indicate a signal to Watch Dog.
If the Watch Dog receives a signal from the System within the programmed time interval, it understands that system is working fine and it restarts it’s timer to receive the next signal.
If the Watch Dog does not receive any signal from the System within the programmed interval, it understands that System has hung and it resets the System automatically. This way, the System comes out of the hung state and starts working as expected.
If the Watch Dog Timer is not there, System will never come out of the hung state.
Watch Dog Timer requires two interfaces:
- APB Interface to program the timeout value.
- System Interface to get signal from the System and to generate reset.
Watch Dog Timer works on a Finite State Machine and the possible states are:
- NO_ACTIVITY — WDT is waiting for an activity signal from the System.
- SYSRST — WDT has hit timeout and still no activity signal from the system. So, it issues Reset Signal.
- ACTIVITY — WDT has received an activity signal from the system within the timeout interval.
Click here for the verilog implementation of Watch Dog Timer.
