Memory Hierarchy

Wei zen Liu
Sep 7, 2018 · 3 min read

Static RAM 1 bit takes 6T(transistor)
Dynamic RAM 1 bit takes 2T(transistor)

CPU:
+ — — — — — — — — — +
| ALU -> register |
| | |
| v |
| [L1 cache($)] |
+ — — — — — — — — — +

> register size normally 4KB
> L1 size from 128KB to 6MB (growing)

Mother Board:

+ — — — — — — — — — — — — +
| [ L2 cache ] |
| [ L3 cache ] |
| . |
| . |
| . |
| [ LLC ] |
| |
| Main memory |
| [bus controller] |
+ — — — — — — — — — — — — +
> cache size goes bigger and bigger
> bus controller who accepted data from the CPU side to be moved to the peripherals side.
Outer Interface (usually): bus (PCIE, SATA,…)
^
|
v
+ — — — — — +
| Storage | (nonvolatile)
+ — — — — — +
+ — — — — — +
| Storage | contains
+ — — — — — +
+— — — — — — — — — — — — — -+
| [micro processor] |
| ^ ^ |
| | | |
| [ROM] v |
| 放firmware [DRAM] |
| 用flash製作 |
| [Disk, memory array] |
+ — — — — — — — — — — — — — +
```

Sequential access(循序存取)
Random access(隨機存取)

磁帶(tape) 為 Sequential access 代表,但無法使用隨機存取。此外,磁帶在不頻繁讀取下,可長期保存資料。
HDD 半循序半隨機
SMR 半循序半隨機(循序>隨機) *大量濫用隨機造成效能衰退*

non volatile memory

  1. NAND flash memory
  2. phase-change memory:
    相變記憶體(crystalline, amorphous)
  3. MRAM
  4. NRAM
  5. RRAM
  6. RERAM
  7. STTRAM
  8. Domain wall RAM
  9. Skyrmion memory
    藉由改變資料位置做寫入、讀取,方便插入改寫單一bit
    因計算模型改變,需要重新設計系統

Cache:

+--+
|__| cacheline block
|__|
|__|
|__|
|__|
+__+
  • FA cache
  • SA cache
  • DM cache → One memory

北科理組文青蘿莉控’s 筆記空間

Data Engineering and Storage Lab, NTUT EE && QA, BOSCH

Wei zen Liu

Written by

Front-end developer / Mobile application developer, Study in NTUT. Skills: Html / SCSS / Javascript(es6) / gulp.js / Vue.js / Git / bash / linux / C / C++ /

北科理組文青蘿莉控’s 筆記空間

Data Engineering and Storage Lab, NTUT EE && QA, BOSCH

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