Memory Hierarchy
Sep 7, 2018 · 3 min read
Static RAM 1 bit takes 6T(transistor)
Dynamic RAM 1 bit takes 2T(transistor)
CPU:
+ — — — — — — — — — +
| ALU -> register |
| | |
| v |
| [L1 cache($)] |
+ — — — — — — — — — +> register size normally 4KB
> L1 size from 128KB to 6MB (growing)
Mother Board:
+ — — — — — — — — — — — — +
| [ L2 cache ] |
| [ L3 cache ] |
| . |
| . |
| . |
| [ LLC ] |
| |
| Main memory |
| [bus controller] |
+ — — — — — — — — — — — — +> cache size goes bigger and bigger
> bus controller who accepted data from the CPU side to be moved to the peripherals side.Outer Interface (usually): bus (PCIE, SATA,…)
^
|
v
+ — — — — — +
| Storage | (nonvolatile)
+ — — — — — ++ — — — — — +
| Storage | contains
+ — — — — — ++— — — — — — — — — — — — — -+
| [micro processor] |
| ^ ^ |
| | | |
| [ROM] v |
| 放firmware [DRAM] |
| 用flash製作 |
| [Disk, memory array] |
+ — — — — — — — — — — — — — +
```
Sequential access(循序存取)
Random access(隨機存取)
磁帶(tape) 為 Sequential access 代表,但無法使用隨機存取。此外,磁帶在不頻繁讀取下,可長期保存資料。
HDD 半循序半隨機
SMR 半循序半隨機(循序>隨機) *大量濫用隨機造成效能衰退*
non volatile memory
- NAND flash memory
- phase-change memory:
相變記憶體(crystalline, amorphous) - MRAM
- NRAM
- RRAM
- RERAM
- STTRAM
- Domain wall RAM
- Skyrmion memory
藉由改變資料位置做寫入、讀取,方便插入改寫單一bit
因計算模型改變,需要重新設計系統
Cache:
+--+
|__| cacheline block
|__|
|__|
|__|
|__|
+__+- FA cache
- SA cache
- DM cache → One memory

