Vitis HLS

Photo by Holger Link on Unsplash

install Vitis:

Downloads

github vitis/HLS example:

Xilinx/HLS-Tiny-Tutorials

設定vitis環境變數:

source /path-to-vitis/2019.2/settings.sh

example: coding_loop_functions

run command: vitis_hls -f run_hls.tcl 執行 command-line synthesis

完成後 多一個folder: proj_loop_functions 存放solution

打開HLS GUI: vitis_hls

查看 proj_loop_functions:

點選Solution Settings: 點選 Vitis Bottom Up Flow

再一次synthesis 完成後 產生 kernel.xml

export RTL: format selection- Vitis kernel.xo

export完成後 產生 xilinx object file: export.xo 以便結合application

export RTL: format selection- vivado ip, 完成後產生 export.zip

參考:

MicroZed Chronicles: Vitis HLS

Building the FPGA Binary