Diving into JTAG protocol. Part 4 — BSDL
Diving into JTAG protocol. Part 1 — Overview.
Diving into JTAG protocol. Part 2 — Debugging.
Diving into JTAG protocol. Part 3 — Boundary Scan.
In the last article, I said “The structure of the boundary scan chain and the instruction set is described in a special .bsd file with the Boundary Scan Description Language (BSDL)". Well, it's time to take a closer look at this file and language.
Files with the .bsd extension describes how to interface with a particular chip using the JTAG interface in the context of PCB and chip boundary-scan testing. Here are the main functions of these files:
- Chip Configuration Description: The file provides a detailed description of the chip pin configuration, including which pins support JTAG.
- Testing and Diagnostics Support: These are used to support testing the PCB for shorts, open circuits, and other common problems. This is especially useful for verifying that components are properly mounted on the board.
- Test Automation: This allows you to automate the testing process by providing the necessary information to the software that controls the test equipment.
- Portability of tests: Since BSDL is based on a standard, the files can be used with a variety of hardware and software that supports the standard, providing a high degree of test portability.
These files are a key component in the testing process of electronic devices, especially in complex systems where accurate and efficient component testing is important.
BSDL is a subset of VHDL which is a hardware description language that describes how a particular JTAG device needs be be implemented for boundary scan.
One of the major uses of BSDL is as an enabler for the development of tools to automate the testing process based on IEEE 1149.1. Tools developed to support the standard can control the TAP if they know how the boundary-scan architecture was implemented in the device. Tools can also control the I/O pins of the device. BSDL provides a standard machine and human-readable data format for describing how IEEE 1149.1 is implemented in a device.
Let’s take a look at the format and syntax of BSDL files.
Syntax
A BSDL description for a device consists of the following elements:
- Entity Descriptions
- Generic Parameter
- Logical Port Description
- Use Statements
- Pin Mapping(s)
- Scan Port Identification
- IDCODE Register Description
- Instruction Register Description
- Register Access Description
- Boundary Register Description
Entity Descriptions
The entity statement names the entity, such as the device name (e.g., STM32F405_415_407_417_LQFP100). An entity description begins with a entity statement and terminates with a end statement:
All of the attributes and descriptions listed below can be located within this block.
This structure allows the device to be described for testing, debugging, and diagnostic purposes, providing the necessary information for tools and equipment utilizing boundary scan technology.
Generic Parameter
This keyword is used to define a parameter that can be changed when implementing the description in a particular device.
In this example, PHYSICAL_PIN_MAP is a generic parameter that defines the chip body type, which will default to the value "DW".
Logical Port Description
The port description gives logical names to the I/O pins and defines their function as input, output, bidirectional, and so on.
The port block contains both "useful" pins of the chip and the JTAG pins, as well as power, ground, and missing pins - pins that are not supposed to be connected to the chip
If the port is a single port, it is marked as bit. If it is a bus, it is labeled as bit_vector(X to Y). Inputs are in, outputs are out, bidirectional lines are inout. Power/ground lines as well as analog I/O and pins not connected to the crystal are marked as linkage.
Use Statements
The use statement is used to indicate that a particular package or library will be used in the current context.
For example:
Indicates that this file uses the IEEE 1149.1 1994 version of the IEEE 1149.1 standard library. In the BSDL context, this expression indicates that the definitions and constructs provided in the 1994 IEEE 1149.1 standard are used to describe the boundary scan behavior. This is to ensure that the description is compatible with tools supporting that standard.
Pin Mapping(s)
This element provides a mapping of logical signals from the Logical Port Description section onto the physical pins of a particular device package. This is necessary because the logical signals of a chip may be the same, but the specific pins are different for different packages.
The distribution of single pins is quite transparent: one logic name — one pin:
The buses are described next way:
Scan Port Identification
The scan port identification statements define the device’s TAP.
Values: TAP_SCAN_CLOCK, TAP_SCAN_IN, TAP_SCAN_OUT, TAP_SCAN_MODE - constants defining standard JTAG signals. Values: TCK, TDI, TDO, TMS are the port names defined in the Pin Mapping(s) section for a particular chip. The value TRUE indicates active use of this port.
Additionally, the TAP_SCAN_CLOCK attribute specifies the maximum frequency of the clock signal, in this example, it is 10 MHz, and the signal is active on both clock edges (rising and falling). Only the BOTH parameter is used for the clock signal, but in general, the following parameters can also be used for signals: RISING or FALLING.
IDCODE Register Description
The IDCODE_REGISTER attribute is used to define the IDCODE register of the chip. This attribute is part of the IEEE 1149.1 (JTAG) specification.
Example:
Instruction Register Description
The Instruction Register description identifies the device-dependent characteristics of the Instruction Register.
The INSTRUCTION_LENGTH attribute defines the length of the IR register in bits.
The INSTRUCTION_OPCODE an attribute defines the command codes.
The INSTRUCTION_CAPTURE attribute defines the value that will be loaded into the shift register when TAP enters the Capture-IR state, in other words, this attribute specifies what the instruction register is initialized with.
Register Access Description
The register access defines which register is placed between TDI and TDO for each instruction.
As discussed in Part 1, various codes placed in the instruction register can select various internal registers as data registers: BYPASS, IDCODE, BSR. The REGISTER_ACCESS attribute determines which instruction will connect which register as a data register.
Similar to instructions that may be standard, or may be unique to a particular chip manufacturer (or a particular model), the JTAG module’s plug-in registers may not be limited to a list of DEVICE_ID, BYPASS, and BOUNDARY. And by entering the MY_INSTRUCTION_OPCODE instruction in the INSTRUCTION_OPCODE attribute, it is possible to tell the control software in the REGISTER_ACCESS attribute that it wishes to connect a non-standard register if the corresponding instruction has been loaded into the instruction register:
Here [8] defines the length of the register.
In addition, you can specify in this attribute what value the register to be connected should be initialized with when the JTAG module enters the Capture-DR state:
Boundary Register Description
The Boundary Register description contains a list of boundary-scan cells, along with information regarding the cell type and associated control.
The BOUNDARY_LENGTH attribute specifies the total number of boundary scan cells.
The BOUNDARY_REGISTER attribute specifies the configuration of each boundary scan cell. Each entry in the attribute represents one cell and includes information about the cell type, associated signal, mode of operation, and optional parameters.
Boundary Register Format:
- Cell Number: The number of the scanning cell and correspondingly the bit number in the
BSRregister. - Cell Type (BC_1, BC_2, etc.): Indicates the cell class defined by IEEE 1149.1. We talked about scan cell types in last article.
- Bound Signal: For example,
Y(1),A(1)specifies the logical name of the signal bound to this cell. - Mode of Operation: Indicates the function the cell performs:
input,output2,output3,bidir,controlorcontrolr. Again, we condemned these functions in a past article. - Additional Parameters: For example, initial values or conditions for specific modes of cell operation. For example, for the STM32F407VG microcontroller, these additional parameters are as follows:
- safe - Specifies the value with which the BSR cell should be loaded for safe operation when the program can select a random value.
- ccel - The control cell number. Specify the control cell that drives the output enabled for this port. As discussed in last week's article, there can be multiple scan cells per controller pin and in such cases usually one of the scan cells is a control cell, which controls the functionality of one or more other cells, for example, by switching them between input and output modes. This parameter indicates the number of the cell which is the control cell for this cell
- disval - defines the value to be written to the control cell for it to switch this port from the "output" state to the "input" state.
- rslt - resulting state. Shows the state of the driver when it is disabled.
Conclusion
In this article, we have covered the BSDL format and syntax that describe the device hardware interface for the JTAG interface including pin map, pin attributes, and control functions which are supplied by the chip vendors. I will use these files in the next article where I will try to describe various JTAG usage scenarios that can be useful for the firmware engineer.
Next part: Diving into JTAG. Part 5 — Usage Scenarios
