Let’s look at the progress of SerDes. Before 2007, SerDes speed grade are below 5Gbps, so it is useful and straightforward to use either IBIS or SPICE model to model IC behavior. Then some standards, like PCIE3 and USB3, apply equalizers to help compensate high frequency loss, AMI model is proposed in IBIS forum to consider real(or mimic) DSP algorithms in simulation phase. To simulate AMI model, ADS 2009 releases a new simulator called “Channel Simulator” to simulate channel together with AMI models. After that, as you may know, ADS Channel Simulator is the Golden-Platform to simulate AMI model.
Now let’s look at the progress of DDR. At first, SerDes and DDR are like two parallel lines. But it changes in 2019 when JEDEC announce to have DFE in DDR5 for high speed. (6400MT/s) So it is more like DDR will follow the path as we have seen in SerDes since 2007.
From the evolution of SerDes( since 2007) and DDR(since 2019), we can have a clear view of HSD progress. As chips getting more complex so that it is difficult or impossible to model the behavior with VI VT table, AMI model is created and defined for simulation purpose. And to simulate AMI model, EDA vendor will provide corresponding tools to simulate AMI model.
Here is the causal relationship: Higher speed grade and big channel loss => Need Equalizer => AMI model for simulating Equalizer or complex DSP => EDA vendor provide tool to simulate AMI model
SerDes: Some high-speed interface (e.g. PCIE2) starts to consider using Equalizer. IBIS forum propose using AMI to model all the DSP algorithms. Then Channel Simulator is introduced in ADS 2009 to support SerDes AMI simulation.
DDR: JEDEC announces DFE usage in DDR5. IBIS forum modifies the AMI structure to support single-end signal. Then Memory Designer is introduced in ADS2019 update1 to support DDR AMI simulation.
