Concurrent-Refresh-Aware DRAM Memory Architecture

The content of this blog is based on the paper CREAM: a Concurrent-Refresh-Aware DRAM Memory Architecture.

DRAM density has been improved dramatically as DRAM technology evolves. The increasing density, especially the increasing row number, introduces a significant refresh penalty because more rows are required to be refreshed at a time. As a result, it takes a longer time and more power to complete a refresh.

Since no memory access is allowed during a refresh, the refresh penalty is no longer trivial and can result in significant performance degradation. So, this paper tries to break the exclusivity of refreshing and memory accesses, by parallelizing refreshing and memory accesses to different parts of the memory.

Sub-Array Level Refresh (SALR)

The range of data movement during a refresh is limited between a sub-array and the corresponding local Sense Amplifier so that it does not induce resource contention with other memory accesses outside the sub-array. Consequently, it provides an opportunity for a bank to serve a refresh and memory access in parallel as long as they can be isolated from each other. This technique is known as sub-array-level refresh and this helps in reducing intrabank-zero-parallelism. SALR can significantly reduce refresh penalty due to the low probability of refresh conflict.

Sub-Rank-Level Refresh (SRLR)

Since all memory operations must abide with the power constraint, no memory access can be issued if all banks are refreshed simultaneously, which in turn kills the memory concurrency. The total current consumed by a refresh is proportional to the number of banks that are refreshed simultaneously. So, SRLR divides all the banks of a rank into sub-ranks and only the banks of this sub-ranks are refreshed simultaneously. As a result, SRLR relaxes or even eliminate the interbank-zero-parallelism because it is no longer necessary to lock all banks during the refresh.

Scheduling of Refreshes

Sub-array round-robin: Row bits are usually placed in the MSBs in the physical address mapping. As a result, it is more likely memory accesses concentrate in a sub-array rather than scatters over the whole bank. So, once a refresh has been completed in a sub-array, the next refresh will move to next sub-array rather than next row in the same sub-array.

Dynamic refresh scheduling: Once a row is accessed its refresh can be scheduled later. According to the status of each sub-rank, the refresh can be executed out of order so that the idle sub-rank is refreshed at first. In this way, the dynamic refresh scheduling policy can further hide the refresh penalty at the subrank level.

Results

The experimental results show that CREAM can improve the performance by 12.9% and 7.1% over the conventional DRAM and the ElasticRefresh DRAM memory, respectively.