El Correo Libre Issue 39

Published in

LibreCores

13 min readJun 8, 2021

European Processor Initiative Tapes-Out First EPAC RISC-V Test Chip

The European Processor Initiative (EPI), a joint project of 28 partners looking to produce European Union-native high-performance computing (HPC) technologies and infrastructure, has announced a milestone: the tape-out of its first RISC-V test chip, EPAC1.0.

“I am really happy how partners with different backgrounds and motivations have been able to collaboratively develop this chip, putting all their efforts towards a collective success,” says project coordinator Jesus Labarta. “It is a fully European design, driven by a vision of throughput-oriented computing and featuring characteristic that will result in high programmer productivity and achieve very high performance at low power and cost. Although just an initial Test Chip, it can be a significant step forward in HPC but also for edge and embedded applications.”

“The key challenge in this design and architecture was not only to achieve highest throughput and low power levels within the accelerators running on more than 1GHz,” adds Norbert Schumann of Fraunhofer IIS, which assisted in the design and finalised the chip for production on GlobalFoundries’ 22FDX node, “but also to be in sync like in a concerto with memory accesses and data transport inside the chip and to the peripherals at rates above 200 Gbit/s.”

The EPAC1.0 design includes four vector-processing micro-tiles combining SemiDynamics’ RISC-V core and a vector processing unit designed by the Barcelona Supercomputer Center (BSC) and the University of Zagreb, a “Home Node” designed by Chalmers, an L2 cache designed by FORTH, a stencil and tensor accelerator (STX) designed by Fraunhofer IIS, ITWM and ETH Zürich, a variable-precision processor (VRP) from CEA LIST, and a network-on-chip and SERDES supplied by EXTOLL.

More information on the test chip’s design is available on the European Processor Initiative website.

Efabless, SkyWater Launch chipIgnite to Bring ASIC Production to All

Following on from the Open PDK MPW-ONE and MPW-TWO shuttles, which saw free and open-source hardware projects invited to have their designs built in silicon on SkyWater’s 130nm CMOS platform, Efabless has announced it is extending the programme to commercial and closed-source projects with chipIgnite — offering production at $9,750 per project.

Like the shuttles contributed as part of SkyWater’s Open PDK, the chipIgnite designs are produced on a 130nm CMOS process with 10mm² of available project area. The starting price of $9,750 includes a choice of 100 QFN or 300 WCSP chips along with five evaluation boards; those looking for higher volume production can apply for 1,000 WCSP parts for $20 each.

“The chipIgnite program offers unique value to the designer which includes not only low-cost manufacturing, but also a development board and firmware stack to simplify design validation and test,” says Efabless of its launch. “All projects created as part of the chipIgnite program will utilise a full chip reference design template that implements the physical IO for the chip as well as provides a common management area to support test and evaluation of the user’s design.

“The program also includes an optional automated open source design flow for implementing projects that enables users to generate layouts for their digital projects from RTL. The chipIgnite program will provide users a guaranteed reservation to ensure their project is included.”

“I am excited to see the chipIgnite programme offered by Efabless to include many different collaborative IP developers to prove new ideas,” says CHIPS Alliance general manager Rob Mains of the move. “The platform alleviates the barriers to entry into chip design and allows for ready exploration of many concepts.”

More information is available on the chipIgnite site, with 19 of the first shuttle’s 40 project slots already reserved ahead of tape-out on the 18th of June. Those with free and open source projects, meanwhile, should look to the Open MPW Shuttle Programme, where the production costs are covered by Google.

Michael Schröder Gives Donald Knuth’s MIX Computer the FPGA Treatment

Developer Michael Schröder has turned to a classic text to provide inspiration for his latest creation: Donald Knuth’s The Art of Computer Programming Volume 1, taking the MIX computer concept and implementing it on an FPGA.

“Have you ever heard of Don Knuth’s (hypothetical) first polyunsaturated computer MIX, the 1009? In this project,” Michael writes by way of introduction, “we will build a binary version of the MIX-Computer as described in The Art of Computer Programming, Vol. 1 by Donald E. Knuth, running on an FPGA-board.

“The presented implementation is based on the FPGA development board iCE40HX8K-EVB from the company Olimex Ltd., which has the nice property of being completely open source. The whole project uses only FOSS free and open source hard- and software, so everybody can build their own MIX following the instructions in build.”

First published in 1968 and as-yet uncompleted, Donald Knuth’s The Art of Computer Programming monograph is a seminal series — and one which took the interesting approach of defining its own computer, the MIX, with its own assembly language. While the books have begun a shift to a 64-bit RISC variant dubbed MMIX, Michael’s implementation focuses on the original MIX.

Full details are available on Michael’s GitLab repository, along with complete source code published under the GNU General Public Licence 3.

RISC-V International Launches Development Partner Programme

RISC-V International has announced a new model for contribution to the open-source project which bears its name and lives under its stewardship: the RISC-V Development Partner Programme.

“I was talking with the key architects. In addition to designing the ISA, they were only a few architects in each of their companies designing the microarchitecture and end products,” RISC-V chief technology officer Mark Himelstein explains of the reason behind the new contribution model. “They barely had enough time to contribute to the ISA efforts let alone work on ecosystem pieces like compilers, operating systems, or architecture tests.

“Coming up with a programme where we could partition the work the task groups need, free up the architects to do architecture, engage more contributors, and recognize the efforts of the organizations seemed like a great idea to try. And the rest is history!”

Those contributing under the new programme will, RISC-V International explains, “independently contribute their engineering support for RISC-V initiatives through leadership, engineering, and resources to drive specific technical deliverables that benefit the RISC-V ecosystem.” The overall aim: to “streamline collaboration while advancing projects the RISC-V Task Groups have identified for extension ratification.”

More information on the programme, which lists the Chinese Academy of Sciences, ICT, ISCAS, RIOS, and the Indian Institute of Technology Madras (IIT Madras) as its initial members, can be found on the RISC-V website.

OpenPOWER Foundation Launches the “First Ever” Open BMC: LibreBMC

The OpenPOWER Foundation has announced the launch of a working group for the production of what it claims is the “first ever baseboard management controller with completely open-source software and hardware,” the LibreBMC.

“The BMC is a critical component in IT infrastructure and is way past due for open collaboration and innovation,” claims James Kulina, executive director at the OpenPOWER Foundation, of the reason behind the project’s launch. “Moving down the stack and open sourcing technology at the silicon level is the logical next step. LibreBMC will enable improved performance, reliability, customization, and security.”

“We are happy to be able to contribute our experience in open source hardware, software tools and IP to LibreBMC,” adds Michael Gielda, vice-president for business development at project partner Antmicro. “Open and secure server solutions allow us to bring scalable and open flows to areas ranging from AI and software to ASIC and FPGA development, and we strongly believe that our customers’ server rooms will get an open source-driven innovation boost with LibreBMC.”

The LibreBMC project will see the Antmicro produce an add-in card based on the Open Compute Project’s DC-SCM specification, built using completely open-source tooling including SymbiFlow and implementing Enjoy-Digital’s LiteX system-on-chip. “We originally developed LiteX for internal needs at Enjoy-Digital,” LiteX maintainer Florent Kermarrec explains. “We’re glad to see it used to enable the development of new open-hardware technologies like LibreBMC.”

Other project collaborators include Google, Yadro, IBM, and Raptor Computing Systems — the latter of which was already working on its own fully-open BMC under the codename Kestrel, running a custom Zephyr-based operating system in place of LibreBMC’s OpenBMC.

More information, and a link to the Working Group, is available on the OpenPOWER Foundation website.

Antmicro, Western Digital Add Dynamic Scheduling to Verilator En-Route to UVM

Antmicro and Western Digital have collaborated to add dynamic scheduling to Verilator, as part of a roadmap to open-source Universal Verification Methodology (UVM) — “historically,” the company claims. “missing from the open source landscape.”

“While new, open source approaches to verification have emerged that include the excellent Python-based Cocotb (that we also use and support) maintained by FOSSi Foundation,” Antmicro explains, “not everyone can easily adopt it, especially in long-running projects and existing codebases that use a different verification approach.

“Leading the efforts towards comprehensive UVM/SystemVerilog support in open source tools, we have been gradually completing milestones, getting closer to what will essentially be a modular, collaboration-driven chips design methodology/workflow. Some examples of our activity in this space include enabling open source synthesis and simulation of the Ibex CPU in Verilator/Yosys via UHDM/Surelog, and the most recent joint project with Western Digital in which we have developed dynamic scheduling in Verilator.”

Part of what Antmicro describes as “a wider, long-term effort” including Google and other CHIPS Alliance members towards supporting UVM/SystemVerilog in open-source tools, the project has extended Verilator’s scheduler. “Verilator’s original scheduler [is] running everything sequentially,” Antmicro explains, “which in general is not a bad approach but can get you only so far without actually executing the code in parallel.

“To run proper UVM testbenches in Verilator, we had to be able to properly handle language constructs specifically designed for use in simulation. Those features include delay statements, forks, wait statements and events. To achieve all of this, we needed to add a proof-of-concept dynamic scheduler to Verilator.”

A full write-up of the project is available on the Antmicro website, while source code for the dynamic scheduler plus examples is available on the project’s GitHub repository under the Apache Licence 2.0.

Antmicro Launches Open Source Portal to Showcase its Projects

To better showcase its various open-source efforts, ranging from application-specific integrated circuits (ASICs) through to cloud systems, Antmicro has launched a dedicated portal — providing a one-stop site for inspiration on a range of topics.

“For more than a decade we’ve been providing commercial support and engineering services around open source software and hardware to our customers, building cutting-edge computer systems for industries such as medical, automotive, robotics, aerospace and manufacturing,” the company boasts. “Our development spans the whole technology stack, from ASIC and FPGA, through hardware platforms, to edge AI software, up to complex cloud systems and tooling ecosystems. We’ve also become members of the most notable open source-oriented organisations and are leading innovators in embedded systems and machine vision.

“Today we are happy to announce the new Antmicro Open Source Portal where you can take a tour of our open source projects, learn more about our mission and ways in which our technologies could be used to help you build your next-gen product.”

The portal site showcases all of Antmicro’s open-source projects in five key fields: ASIC and FPGA, which the company says is “heading towards a revolution which will bring about much more modular, software-driven and reusable systems — all enabled by open source”; development platforms, including its ARVSOM system-on-module; edge artificial intelligence; and cloud systems, including Renode and related continuous integration (CI) environments.

The Antmicro Open Source Portal is live now on its dedicated subdomain.

Graphics Gremlin Puts an FPGA on your ISA Bus as an Open-Source Graphics Card

Vintage computing enthusiast Eric “Tube Time” Schlaepfer has released an open-source project designed to bring classic computers based around the Industry Standard Architecture (ISA) bus back to life by replacing dead or simply difficult-to-use MDA and CGA graphics cards.

“The Graphics Gremlin is an FPGA-based ISA video card specifically designed to emulate certain old video standards,” Eric explains. “This initial release emulates the original IBM PC monochrome graphics adapter (MDA) as well as the original IBM color graphics adapter (CGA). Since the logic is defined by the bitstream loaded into the FPGA, new emulations may be available in the future to support other video standards.

“But why emulate an old video card when they are still fairly easy to find online? Cards aren’t hard to find, but monitors that can sync to the unusual frequencies used by MDA (18KHz) and CGA (15KHz) are much harder to find, and these frequencies are rarely supported by modern LCD monitors or video capture hardware.

“For both MDA and CGA,” Eric continues. “the Graphics Gremlin has a VGA port that can deliver video running at standard (31kHz) frequencies that are well supported by LCD monitors, VGA-to-HDMI converters, and USB capture devices.”

The Graphics Gremlin hardware is a two-layer board built around a Lattice Semiconductor iCE40HX4K FPGA, running Verilog built through Project IceStorm and NextPNR. Everything, including schematics and a bill of material, is made available under the Creative Commons Attribution-ShareAlike 4.0 International Licence on Eric’s GitHub repository.

Gatecat’s HRT PoC Gives FPGAs “Hot Reconfiguration” Capabilities

Pseudonymous FPGA developer Gatecat has released a proof-of-concept project which adds basic “edit and continue” capabilities to FPGAs: Hot ReconfiguraTion, or HRT.

“This is a very ugly proof-of-concept of loading a modified FPGA design without losing state, using the partial reconfiguration-like features of the [Lattice Semiconductor] ECP5,” Gatecat explains of the project. “It includes a small demo that turns an up counter into a down counter, keeping the count value.

“Currently it is only suited for demos of this size and is a long way from something useful, but is a taste of the future where FPGAs have edit-and-continue support. More complex designs [are] probably a year’s work away.”

The project is similar in concept to an earlier effort by Sylvain Lefebvre, Juanma Rico, and Unai Martinez-Corral, showcased in last month’s newsletter, in which a Lattice iCE40 cycles through eight separate designs loaded from its SPI flash. “Each design goes back to the bootloader on button press,” Sylvain explained at the time. “This is faster than swapping entire designs as ‘only’ the first 4kB are updated.”

A video of HRT in action is available on Gatecat’s Twitter account, while the source code has been published to GitHub under an unspecified licence.

Stephen Marz Offers Five Tips for Writing RISC-V Assembly

Educator Stephen Marz has published a guide to writing RISC-V assembly, offering five key tips to what he describes as “the art of writing assembly” for the free and open-source architecture.

“Writing assembly is itself an art,” Stephen explains. “When C, C++, or any other language is compiled, the compiler determines the art of writing assembly. However, this time, we will some of the techniques and decisions we can make to write these ourselves.

“We will use RISC-V to see how to design logic, write up the logic, and translate the logic into assembly.”

Designed for beginners, Stephen’s guide is broken into five key “tips”: designing the logic in a comfortable language, potentially even pseudocode; taking small bites and testing as you go along; to “know your role,” in particular paying attention to the order of operations; knowing how to call a function; and documentation, a key piece of advice for any project.

The full guide is available on Stephen’s website now.