El Correo Libre Issue 42

Published in

LibreCores

14 min readSep 14, 2021

Google Summer of Code (GSoC) 2021 was a Success!

As summer comes to an end, we have also completed this year’s iteration of Google Summer of Code (GSoC). We at FOSSi Foundation are delighted to say that all of our students this summer successfully completed their projects.

For multiple years now, FOSSi Foundation has acted as an umbrella organization for GSoC projects and this year we were particularly excited to have eleven students receiving mentorship from our community.

All projects were mentored by trusted community members, including seven first-time FOSSi GSoC mentors, and we are extremely happy with how well the projects went! We owe a big thank you to all students and mentors: Thanks to you, the free and open source silicon ecosystem is in a better place than before.

Below is a collection of links to our students’ final project blog posts. Please have a read and join us in congratulating them on such a successful summer! We hope to see you all again for next year’s GSoC.

FuseSoC Integration of BaseJump STL (Adithya Sunil)
Mentored by Olof Kindgren, Dan Petrisko, and Michael Taylor
Adithya’s blog post

Parallelising Verilog RTL Simulations Using MPI (Guillem Lopez Paradis)
Mentored by Jonathan Balkind and Stefan Wallentowitz
Guillem’s blog post

Formal verification of mor1kx (Harshitha S)
Mentored by Stafford Horne and Stefan Wallentowitz
Harshitha’s blog post

Virtual FPGA Lab (Bala Dhinesh)
Mentored by Kunal Ghosh, Ákos Hadnagy, and Steve Hoover
Bala’s blog post

M-extension support for SERV (Zeeshan Rafique)
Mentored by Olof Kindgren and Stefan Wallentowitz
Zeeshan’s blog post

Block-Based Circuit Design (Ninad Jangle)
Mentored by Steve Hoover, Gayatri Mehta, and Adam Ratzman
Ninad’s blog post

Multi-Level TLB Support for Ariane Core (Nazerke Turtayeva)
Mentored by Nils Wistoff and Jonathan Balkind
Nazerke’s blog post

WARP-V manycore in the Cloud (Vineet Jain)
Mentored by Ákos Hadnagy, Steve Hoover, and Shivam Potdar
Vineet’s blog post

SkyParrot: Preparing BlackParrot for Open-Source Fabrication using Google-Skywater 130nm PDK (Lakshmi S)
Mentored by Dan Petrisko and Michael Taylor
Lakshmi’s blog post

Bring up CV32E40P AI accelerator on FPGA (Veronia Iskandar)
Mentored by Jeremy Bennett and William Jones
Veronia’s blog post

TensorCore Extension for Deep Learning (Nitin Mishra)
Mentored by Steve Hoover and Theodore Omtzigt
Nitin’s blog post

-Jonathan Balkind, Director, FOSSi Foundation

Open Compute Project 2.0 Launches with a Promise to Seed Innovation in Open Silicon

The Open Compute Project, launched by Facebook back in 2011, has announced a new phase it has dubbed OCP 2.0 — and it comes with a pledge to “seed future innovation” in open silicon efforts.

“10 years ago, when OCP started, there were just 5 members whose vision was to drive a hardware movement that would inspire the same creativity and collaboration we saw in open-source software,” incoming chair and board president Rebecca Weekly recalls.

“Over the last 10 years, significant advancements have been made in open compute standards with the formation of multiple working groups delivering over 350 collaborations. As we look to the future, the Board sees computation requiring increasingly heterogeneous and disaggregated solutions, and it is more important than ever for the ecosystem to come together to reimagine hardware and its ability to address this growing complexity with sustainable, secure and manageable practices.”

The way the organisation aims “reimagine hardware” is with OCP 2.0, which includes a move beyond open-standard motherboards and server systems and into the silicon itself. “[OCP 2.0 will] define interfaces for future co-packaging,” Rebecca claims, “to enable best-in-class components from the silicon up and drive tools and reference platform standards.”

Other “seed” projects mentioned include optics, artificial intelligence and machine learning, and “best-in-class advanced cooling solutions, sustainable immersion cooling, and cold plate designs that support use cases from cloud to edge.”

Rebecca’s full blog post is available on the Open Compute Project website.

Google, Antmicro Detail LiteX Rowhammer DDR Test Platform

Antmicro has published details on an open test platform, developed in partnership with Google, for the Rowhammer family of vulnerabilities in dynamic RAM: The LiteX Rowhammer Tester.

“Rowhammer is a hardware vulnerability that affects DRAM memory chips and can be exploited to modify memory contents, potentially providing root access to the system,” explains Antmicro. “It occurs because Dynamic RAM consists of multiple memory cells packed tightly together and specific access patterns can cause unwanted effects that propagate to nearby memory cells and cause bit-flips in cells which have not been accessed by the attacker.

“The Rowhammer Tester platform was developed for and with Google, who just like Antmicro believe that open source, well documented technical infrastructure is critical in speeding up research and increasing collaboration with the industry. In this case, we wanted to enable the memory security researchers as well manufacturers to have access to a flexible platform for experimenting with new types of attacks and finding better Rowhammer mitigation techniques.”

Designed to provide an FPGA-based testing platform with full control, the tester uses a LiteDRAM controller and a VexRiscV CPU alongside a bulk transfer module and a payload executer — the latter adding finer-grained control of the test process.

The source code for the tester is published on GitHub under the permissive Apache 2.0 licence, alongside a prebuilt image for setting up the Xilinx Zynq UltraScale+ ZCU104 Evaluation Kit as a test platform.

Sam Zeloof’s Garage Semiconductor Fab Outputs 12 10µm 100-Transistor Chips

Self-described “maker of things” Sam Zeloof has been continuing his experimentation with a home-brew semiconductor fab, and its latest output is little short of incredible: 12 chips of 100 transistors each, built on a 10µm process.

“The Z1 [chip made in 2018] had 6 transistors and was a great test chip to develop all the processes and equipment,” Sam explains. “The Z2 has 100 transistors on a 10µm polysilicon gate process — [the] same technology as Intel’s first processor.

“My chip is a simple 10×10 array of transistors to test, characterize, and tweak the process but this is a huge step closer to more advanced DIY computer chips. The Intel 4004 has 2,200 transistors and I’ve now made 1,200 on the same piece of silicon.”

Sam’s first chip, covered way back in Issue 3, was constructed at home using a metal gate process — and despite its limited number of transistors found a home in a selection of practical projects including a guitar distortion pedal and a LED blinker.

“By switching to a polysilicon gate process,” Sam explains, “I get a ton of performance benefits (self aligned gate means lower overlap capacitances) including a much lower Vth which makes these chips compatible with 2.5V and 3.3V logic levels. Now we know that it’s possible to make really good transistors with impure chemicals, no cleanroom, and home-made equipment. Of course, yield and process repeatability are diminished.”

Sam’s full write-up is available on his website, alongside a companion video on YouTube.

Scientists Unveil RiskiM, a Hardware Platform for OS Kernel Integrity on RISC-V

Computer scientists at Pusan National University and Seoul National University have published a paper detailing RiskiM, a hardware platform designed to guarantee the kernel integrity of an operating system running on RISC-V.

“The OS kernel is typically presumed as a trusted computing base in most computing systems. However, it also implies that once an attacker takes control of the OS kernel, the attacker can seize the entire system,” the researchers write.

“In this paper, we introduce RiskiM, a new hardware-based monitoring platform to ensure kernel integrity from outside the host system. To deliver the inner state of the host to RiskiM, we have devised a hardware interface architecture, called PEMI. Through PEMI, RiskiM is supplied with all internal states of the host system essential for fulfilling its monitoring task to protect the kernel.

“To empirically validate our monitoring platform’s security strength and performance, we have fully implemented PEMI and RiskiM on a RISC-V based processor and FPGA, respectively. Our experiments show that RiskiM succeeds in the host kernel protection by detecting even the advanced attacks which could circumvent previous solutions, yet suffering from virtually no aforementioned side effects.”

The paper has been published under open-access terms in the journal Electronics.

FPGA Tooling Interoperability Gets a Boost from SymbiFlow’s FPGA Interchange Format

In another of its partnerships with Google, Antmicro has begun work on creating a standardised interchange format designed to make it easier to work with different FPGA tool chains: The SymbiFlow FPGA Interchange Format.

“FPGA toolchains are not trivial as they comprise several elements which themselves can be quite complex,” Antmicro explains of the problem under investigation. “Roughly speaking, you can divide the process of “compiling” FPGA-targeted code in a Hardware Description Language (HDL) into three stages: synthesis, place and route, bitstream generation.

“A standard format could provide a common description of the various architectures and serve as a bridge between the multitude of open source and closed proprietary tools that deal with the entire process or parts thereof, including the open source Yosys for synthesis and VtR and nextpnr for place and route, to relevant vendor tooling from Xilinx, Intel, Lattice, QuickLogic, etc.”

That standard format: SymbiFlow FPGA Interchange Format, designed as a “unified framework that, by lowering the entry barriers, lets developers swiftly move from one tool to another with virtually no effort.”

The format provides three key descriptors: Device resources, including the FPGA’s internal structure and cell libraries; a logical post-synthesis netlist; and a physical netlist. “The FPGA Interchange format in its current form focuses on the only architecture type in mainstream use on the market today,” Antmicro admits, “namely island-based (also called tile-based) FPGAs: two-dimensional arrays of reconfigurable logic blocks, hard blocks, switch blocks and input-output blocks. This allows the standard to reach a level of universality and conciseness which makes it easy to work with, adopt and implement.”

More information is available on the Antmicro blog and in the SymbiFlow FPGA Interchange Format documentation.

European Commission Predicts Open-Source Hardware will become a “Cornerstone”

The European Commission (EC) has published a report into the impact of open source software and hardware (OSS and OSH) on the European economy, labelling both as a “public good” while also highlighting the potential for open-source hardware to become a “cornerstone” of technological innovation.

“The main breakthrough of the study,” the organisation notes, “is the identification of open source as a public good. This shows a change of paradigm from the previous irreconcilable difference between closed and open source, and points to a new era in which digital businesses are built using open source assets. This information is essential to develop policy actions in the field.

“If OSH is to follow the same development as OSS, it could constitute a cornerstone of the future Internet of Things (IoT), the future of computing and the digital transformation of the European industry at the end of the digital decade.”

The report further details how both open-source software and hardware can “provide control over technologies” and help European nations “reduce the dependency on vendors of specific proprietary technologies and software.”

The full 390-page report is available on the European Commission website now, under a permissive Creative Commons licence.

Open Implementation Brings “All the Polynomial Multiplication You Need” to RISC-V

A team of researchers from Hansung University and Gachon University have published a paper on polynomial multiplication methods for RISC-V cores — and has released its proposed implementation into the public domain.

“Polynomial multiplication is a core operation for public key cryptography, such as pre-quantum cryptography (e.g. elliptic curve cryptography) and post-quantum cryptography (e.g. code-based cryptography and multivariate-based cryptography),” the researchers explain. “For this reason, the efficient and secure implementation of polynomial multiplication has been actively conducted for high availability and security level in application services.

“ In this paper, we present all polynomial multiplication methods on modern 32-bit RISC-V processors. We re-designed expensive implementations of polynomial multiplication on legacy microcontrollers (e.g. 8-bit AVR, 16-bit MSP, and 32-bit ARM) for new instruction sets of 32 bit RISC-V processors. Secondly, we suggest the optimal operand length for each polynomial multiplication on 32-bit RISC-V processors. With this implementation technique and Karatsuba algorithm, we achieved scalable features, which ensures the polynomial multiplication in any operand lengths with reasonably fast performance.”

As a further step, the team proposed instruction set extensions for RISC-V which would allow for the optimal implementation of polynomial multiplication on 32-bit cores — and went a step further, releasing its proposed implementation under the permissive Apache 2 and MIT licences.

The implementation is available to download from GitHub now, while the paper can be downloaded from the IACR Cryptology ePrint Archive under open access terms.

Public Review Open for Proposed RISC-V Scalar Cryptography Extensions

The RISC-V Cryptography Extensions Task Group has formally opened up its proposed instruction set extensions for public review, in one of the final stages before they are adopted — or not — as official standards.

“This specification has been developed by the RISC-V Cryptography Extensions Task Group under the governance of the Unprivileged and the Security Committees,” says Richard Newell, Group chair and fellow at Microchip.

“During the public review period, corrections, comments, and suggestions, will be gathered for review by the Cryptography task group. Any minor corrections and/or uncontroversial changes will be incorporated into the specification. Any remaining issues or proposed changes will be addressed in the public review summary report.

“If there are no issues that require incompatible changes to the public review specification,” Newell notes, “the unprivileged ISA committee will recommend the updated specifications be approved and ratified by the RISC-V Technical Steering Committee and the RISC-V Board of Directors.”

The proposed extensions, designed to improve performance of a variety of cryptographic operations, cover features including AES encryption and decryption, use of the ShangMi SM4 block cipher and SM3 hash function, crossbar permutation, carry-less multiplication, entropy source operations, and more.

The latest version of the extensions can be found on the RISC-V GitHub repository, under the permissive Creative Commons Attribution 4.0 International licence, while anyone wishing to provide comment is asked to do so on the RISC-V ISA Dev mailing list or GitHub Issues by the end of Sunday the 17th of October 2021.

Clever Hack Puts RISC-V Into VRChat, Running Linux on a Pixel Shader

Developer Stefan Reiter has found an unusual use-case for RISC-V: Running an emulator on a pixel shader in order to successfully boot an operating system in the VRChat software.

“Sometimes you get hit with ideas for side-projects that sound absolutely plausible in your head. The idea grips you, your mind’s eye can practically visualize it already. And then reality strikes, and you realize how utterly insane this would be, and just how much work would need to go into it,” Stefan explains.

“Usually these ideas appear, I enjoy dissecting them for a few days, and then I move on. But sometimes. Sometimes I decide to double down and get Linux running on my graphics card.”

Stefan’s project saw the creation of a pixel shader which runs an RV32ima/su+Zifencei+Zicsr instruction set, and which uses a 2048x2048 texture as 64MB of RAM, in order to implement a computer capable of booting into Linux inside VRChat.

“After a few months of work, I’m now proud to present the worlds first (as far as I know) RISC-V CPU/SoC emulator in an HLSL pixel shader,” Stefan writes, “capable of running up to 250 kHz (on a 2080 Ti) and booting Linux 5.13.5 with MMU support.”

Stefan’s full write-up is available on his blog, while the source code is on GitHub under the permissive MIT licence.

Skudo’s Open-Hardware Kryptor FPGA-stroke-HSM Hits Crowd Supply

Skudo’s security-focused open-hardware Kryptor FPGA development board has launched on Crowd Supply, offering a compact board built around Intel’s Altera MAX10 and designed for hardware security module (HSM) projects.

“Designed with encryption in mind and built around a single, compact Intel/Altera MAX10 FPGA chip,” its creators explain, “Kryptor is a professional FPGA development board capable of offering all the functionality of a dedicated Hardware Security Module (HSM) when running our custom soft-core.

“Combined with that verifiable HSM soft-core, Kryptor brings an easy-to-use, plug-and-play encryption solution to the IoT-developer and maker communities.”

The board includes a MAX10 FPGA with 8k logic elements, 378kB of total internal RAM, 1,376kB of flash, a 100Mhz operating frequency, a range of general-purpose input/output (GPIO) pins, an SPI bus, and a JTAG connector for programming and debugging.

“Everyone who backs the Skudo Kryptor crowdfunding campaign will have the option to download the HSM soft-core free of charge from skudo.tech, along with instructions that walk you through the simple process of flashing that soft-core onto your board (without the need for a JTAG adapter),” the company promises.

“Of course, backers are free to use Kryptor in any way they like. Use it as a MAX10 FPGA development board or load your own soft-core. And you can still load our HSM soft-core, at a later date, using our JTAG adapter board.”

The campaign is live now on Crowd Supply, with physical rewards starting at $129 for a single board with shipping expected to begin in February 2022. While it promises that the device will be open hardware, however, it does not yet appear to have publicly released any source files.