El Correo Libre Issue 46

Published in

LibreCores

12 min readJan 11, 2022

Incredible Hack Implements a CPU in a Modular Analogue Synth

Building a CPU out of discrete digital logic is a right-of-passage for many in the world of free and open source silicon and open hardware, but engineer Kate F. has gone a step further — building a functional CPU using an analogue modular synth.

“I’m using VCV Rack. It’s software simulation for Eurorack modular synthesisers, either in conjunction with, or in place of hardware modules,” Kate explains of the project. “You know the wub wub squelchy analogue sounds and acid bass with LFO fades? It’s for making that sort of stuff.”

What Kate has made, though, doesn’t squelch or wub-wub at all: it’s a CPU.

“First I made a ripple carry adder,” Kate explains. “Then I squished it all together and built an ALU around it. [The] lines here are polyphonic audio, I’m using them to carry eight bits each. Multi-channel attenuverters make for a handy way to set a byte.

“Then i made a register. This uses sample & hold to store an 8-bit value. That’s a snapshot of a voltage, updated by either a rising edge, or level-triggered. Then I made a register bank, indexed by two bits (converted to an analogue level by a DAC.)

“I had to switch from using voltage-controlled amplifiers to boolean AND gates,” Kate adds, “because my bits in registers were fading when I output and re-loaded them. Sort of like every bit has a TTL. It makes computing very exciting. Imagine storing data in a register, but over the course of using it the quality seems to deteriorate and it gets wose an wose, where the stwucture rewerts to a pwoit of utew non swence, an u jus dont wanna wead it anymowre owo. Then I stuck everything together with a bus.”

Kate has a detailed thread on Twitter going into the ins and outs of the project, including plans for adding MIDI input capabilities “and [programming] my CPU with sheet music using Musecore.” VCV Rack patches for the procjet, meanwhile, are available on GitHub under an unspecified open-source licence.

Antmicro, Google Release FPGA-Based Rowhammer Test Kit

Antmicro has announced the continuation of its partnership with Google, releasing a test platform based around the Xilinx Kintex-7 FPGA and aimed at offering testing for the Rowhammer security vulnerability on server-centric DDR4 RDIMM modules.

Antmicro unveiled its original LiteX-based Rowhammer DDR Tester late last year, with the aim of making it possible for memory security researchers and manufacturers to experiment with carrying out — and thwarting — Rowhammer attacks, which address memory available to an attacker in such a way to effect bit-flips in memory to which the attacker should not have access.

“Consumer-facing devices are not the only ones at risk,” Antmicro explains of the reason for extending its work beyond consumer-grade DDR4 modules. “With the growing role of shared compute infrastructure in the data centre, keeping the cloud secure is critical.

“That is why we again teamed up with Google to bring the open source FPGA-based Rowhammer security research methodology to DDR4 RDIMM used in servers by designing a new Kintex-7 platform for that use case specifically, to foster collaboration around what seems to be one of the world’s largest security challenges.”

The open-hardware test platform uses a larger 686-pin Kintex-7 FPGA than the original, to interface with the additional pins of an RDIMM module. The FPGA runs the LiteDRAM open-source memory controller, allowing for easy modification and reconfiguration during testing, and the board accepts a fully multi-chip RDIMM module rather than individual memory ICs.

More details on the design are available on the Antmicro website, with design files and source code available on GitHub under the permissive Apache 2.0 licence.

OpenRISC Port Accepted Upstream for Release in glibc 2.35

OpenRISC maintainer Stafford Horne has announced upstream acceptance of a glibc port, which will bring OpenRISC support to the library from release 2.35 — currently scheduled for release in February 2022.

“The glibc OpenRISC port has just been pushed upstream and shall be included in 2.35,” Stafford announced via Twitter. Thanks for all for the help from Adhemerval Zanella and reviewers; also thanks to Christian Svensson for getting it all started.”

First released in 1987, glibc — the GNU C Library — is a backwards-compatible, portable, and high-performance standard library for ISO C. Its upcoming 2.35 release will include, alongside OpenRISC support, improved handling of huge pages via a new tunable — offering the potential for performance improvements, depending on workload.

“Currently the [status of the] port as of the 2022–01–03 rebasing: there are no known architecture specific test failures,” Stafford wrote in a commit message for the port providing supporting documentation. More details are available on the project’s Git repository.

Article image by Shmuel Csaba Otto Traian, CC-BY-SA 3.0.

Edalize 0.3.0 Brings a New Internal Architecture, Lattice Nexus Backend

Olof Kindgren has announced the release of Edalize 0.3.0, the popular Python-based abstraction library for interacting with electronic design automation (EDA) tools.

“During this development cycle, most of the work has been done under the hood with creating a new internal architecture and refactoring many of the backends,” Olof explains of the new release. Most of those efforts will bear fruit longer term, but we can already today see the initial work on the Flow API, that has been planned for at least two years.

“We also welcome a new backend for Lattice Nexus devices and some miscellaneous feature additions and bug fixes.”

The new release introduces the Flow API, an application programming interface designed to separate the execution of individual EDA tools and the execution of a flow graph into two distinct problems. “There are still a lot of things that need to be properly documented, features to add and many of the existing backends still need to be ported over to the new flow API,” Olof admits, “but the good news is that an initial version of the flow API is shipping with Edalize 0.3.0, so you can try it out right away.

“I hope you all enjoy this new version of Edalize. As always, there’s plenty of things going on and we would love some help, so if you want to get involved you are most welcome to join the chat or look through the code, issues or PRs on GitHub.”

More details on the new release, including the Project Oxide backend for Lattice Nexus devices, a “blinky” example for the new Flow API, and a look at a launcher script for Docker, are available on Olof’s blog.

Hans Baier Releases an Open-Source 32-Channel USB 2.0 Audio Interface

Musician and self-described “computer and electronics nerd” Hans Beier has released an open-source USB 2.0 audio interface supporting 32 channels, designed for use with ADAT optical inputs and outputs at a 48kHz sample rate.

“After a week of intense debugging I finally got all 32 channels of my open source USB2 audio interface working (input + output),” Hans announced via Twitter. “The FIFOs behind the ADAT receivers were too small. Gave them a boost and now all 32 channels seem to be rock solid.”

The project uses, in its initial incarnation, a QMTech Cyclone IV Core Board on a custom carrier board. The present releases uses “around 10k LUT and FF unoptimised,” Hans writes — a figure which “will increase as I add functionality.

“[It] enumerates as [a] class-compliant audio device on Windows and Linux (Mac OS not tested). 2 and 32 channel modes. [It] has a hardware round trip latency (USB out -> ADAT out -> cable -> ADAT in -> USB in) of 2–3 USB2 microframes, which is about 0.25ms to 0.375 ms.”

The gateware, carrier board design, and a 3D-printable case are all available on Hans’ GitHub repository under the CERN Open Hardware Licence Version 2 — Weakly Reciprocal, though Hans warns that “this is still a WIP [Work In Progress] and hardware is still early prototype.”

Zero to ASIC Course Celebrates its Fourth Silicon Tape-Out

Matthew Venn’s popular Zero to ASIC course, which aims to introduce developers to chip design from scratch and which now offers the option to have a design constructed in silicon at SkyWater through the Open MPW Shuttle programme, has celebrated its fourth tape-out.

“I was pretty pleased we managed to get so much in with such little time and for a tape-out date of New Year’s Eve,” Matthew writes. “We had nine submissions from the course, with one demo project from me and a new version of Maximo’s hacksoc. Uri submitted 3 designs including some custom standard cells in the shape of skulls!

“We also implemented the shared SRAM, which means that the group projects have access to a local fast memory (like a blockram on an FPGA).”

The nine projects submitted were: Matthew’s function generator demo; Uri Shaked’s SPELL CPU, skull-shaped SkullFET MOSTFET transistors, and implementation of Conway’s Game of Life ; a PPM coder from Llorens_MRC; a PPM decoder from jospicant; an SPI RAID controller from Dylan Wadler; a seven-segment watch-on-a-chip from Guillem Cabo and Ledoux Louis; and hacksoc by Maximo Balestrini, a hardware implementation of the Hack Computer featured in the NAND to Tetris course.

More details, including links to all nine of the projects, are available on the Zero to ASIC course website.

Antmicro’s Nexys Video-Based SATA Platform Offers a Host for LiteSATA

Antmicro has announced the release of a hardware platform for the SATA storage controller project LiteSATA, powered by a Digilent Nexys Video development board with an Xilinx Artix7 FPGA — and using an open-source toolchain.

“To prove the viability of open source FPGA tools, being able to implement high-speed interfaces to verify how the toolchain handles high-speed transceivers is key,” the company explains. “Thus, a fully open source SATA is a very good target, especially that an open source core, LiteSATA, was available in our favourite open source SoC generator for FPGAs, LiteX. What was missing was a hardware platform, putting it all together, and — of course — tools

“The SATA design we developed is meant to run on top of a Nexys Video board from Digilent, featuring an Artix7 200T Xilinx FPGA, coupled with custom expansion board connected through the FMC connector and hosting an M.2 SSD module. Thanks to the FMC connector on the Nexys Video we achieved a relatively simple and modular hardware setup.”

As well as the open-source hardware expansion board itself, the project includes a LiteX SoC featuring a VexRiscV CPU, LiteDRAM controller, a UART controller, the LiteSATA core, and what Antmicro describes as “a simple BIOS that can perform SATA initialisation and basic read and write operations” on a connected SATA Solid State Drive (SSD).

“The SATA setup proves that high speed protocols can be enabled on mainstream FPGAs such as Xilinx 7-series with an open source toolchain, with Yosys for synthesis and VPR for place and route,” Antmicro writes. “The LiteSATA IP core makes use of so-called GTP hard blocks, and in fact one of the main challenges we dealt with here was enabling these hard blocks in the Artix-7 architecture definition to get an end-to-end open source toolchain.”

More details are available on the company blog, while design files for the expansion board can be found on the project’s GitHub repository under the permissive Apache 2.0 licence.

Ali Ahmed Unveils “Pakistan’s First Completely Open-Source SoC”

Ali Ahmed, PhD, assistant professor at the Usman Institute of Technology (UIT) has announced that Pakistan’s first natively-developed open-source system-on-chip (SoC) is ready to ship — having been put into production at SkyWater as part of Efabless’ first Open MPW Shuttle.

“What a moment for Pakistan and [the] open-source silicon fraternity,” Ali writes. “Proud of being part of [the] first-ever completely open source shuttle programme, MPW-1. Funded and supported by Google , Efabless Corporation, and SkyWater Technology Foundry.

“‘Ghazi’ and ‘Ibtida’ — RISC-V based SoCs are ready to be shipped to Pakistan. The design was done by undergrad students Muhammad Hadir Khan, Zain Khan, Aireen Amir Jalal, Hafiz Wajeh ul Hasan, Sajjad Ahmed, Zeeshan Rafique, and many more. Thanks to Dr. Syed Roomi Naqvi, Dr. Zahir Ali Syed (Late) for enabling and believing in Micro Electronics Research Lab at UIT University.”

Ghazi is a system-on-chip featuring a BrqRV-EB0 RV32IMC core, a RISC-V debug module, SRAM for data and instructions, timer, UART, and general-purpose input/output (GPIO) pins with a wrapper logic layer; Ibtida is described as a “minimal” SoC featuring a Buraq-mini RV32IM core, two blocks of DFFRAM, and GPIO connectivity.

More information is available on Ali’s LinkedIn post, while the source code for both Ghazi and Ibtida are available on the projects’ respective GitHub repositories under the permissive Apache 2.0 licence.

Tom Verbeure Demonstrates “Semihosting” for RISC-V CPUs

Engineer Tom Verbeure has written a guide to “semihosting” a RISC-V CPU on another computer — as a means of avoiding the use of a dedicated hardware block for communication between the two.

“When running code on an embedded CPU, it’s very often helpful to have an interface to a PC to run some kind of console or terminal for control, debugging, and logging,” Tom explains. “A UART is obviously very popular for this, but I often also use a JTAG UART, which can be easier to integrate if you already have a JTAG connection to for FPGA for other reasons.

“But there’s another option that many probably have never heard about. Instead of using a dedicated HW block, it leverages the existing debug infrastructure of the CPU by adding a peculiar software layer on top of the low level debug driver. It’s called semihosting, and it allows the embedded CPU use the host PC as a server for a variety of functions: STDIO read and write, access to the PC file system, time server etc.”

While admitting the approach is “definitely a bit of a hack,” Tom extols its virtue — and says there’s “something magical about a slow embedded CPU with 4kB of RAM commandeering a mighty PC into reading and writing files on its file system.”

Tom’s full write-up is available on his blog, with an example design published to GitHub under a mix of open-source licences.

OpenFPGALoader Hits v0.7.0, Brings Support for Even More FPGA Parts

The openFPGALoader project, which aims to offer a single utility for programming as broad an array of FPGA hardware as possible on Windows, macOS, and Linux, has hit v0.7.0 — bringing with it support for a range of new FPGA parts.

“[The] most notable evolutions: ALL Digilent Arty boards are supported (thanks Tim “Mithro” Ansell); new Cologne Chip GateMate FPGA (thanks Patrick Urban); better SPI flash support,” wrote project maintainer Gwenhael Goavec-Merou of the release.

The latest release of the open-source tool brings with it new support for the Anlogic ELF2 EF2M45, the Cologne Chip GateMate family, the Xilinx Zynq XC7Z010, Titanium Ti60 F225, and all Digilent Arty development boards; these land on top of support for parts including the MacX03D, Coolrunner-II, Spartan3, GW1NSR-4C, and XC95 CLPD range which were added early December in v0.6.0.

Full details are available in the release notes, while the latest source code is available on the project’s GitHub repository under the permissive Apache 2.0 licence.