ICLAB Lab01 Note

Week 2

LAB Description

Topic of this week

1. Introduction to Design Flow
2. Basic Description of Verilog
3. Behavior Models of Combinational Circuit
4. Simulations

Design

Supper MOSFET Calculator (SMC)

Description

Given 6 combinations of width, Vgs and Vds, calculate and sort their drain current or their transconductance based on mode bits.

GitHub

2021_Spring_NCTU_ICLAB/Lab01/

What did I learn this week?

1. Realize Combinational Circuit with Verilog.
2. Verilog Coding Style.
3. Extract the same structure of different formulas to reduce the usage of adders/multipliers/dividers in order to reduce area.

Lecture Note

PPA

Power, Performance, Area.

CISC / RISC

Complex Instruction Set Computer, e.g. x86.
Reduced Instruction Set Computer, e.g. arm.

Profiling

Measure the space/time complexity of a program, find the most time-consuming part of system/algorithm, and implement this part in hardware instead of software.

FPGA

Field-Programmable Gate Array.

Pro. : No fabrication is needed.
Con. : Limited routing resources.

ASIC

Application Specific Integrated Circuit.

1. Cell-based Design Flow
   Use pre-designed logic sells (known as standard cells) and micro cells (e.g. microcontroller). See ICLAB Lab02 Note : Design Flow.
   Pro. : Design speed is fast. Save time, money and reduce risk.
   Con. : Less design freedom.
2. Full-custom Design Flow
   Design every thing by yourself.
   Pro. : Large design freedom.
   Con. : Design speed is slow.

Verilog Note

Continuous vs Procedural

• Continuous Assignment : for wire assignment.
• Procedural Assignment : for reg assignment.

Unsigned vs Signed

• reg type is regard as unsigned in default : automatic 0 extension.
• If there are ONE unsigned operator, the operation will be regard as unsigned.
• automatic signed extension vs manual signed extension :

Shift Operator (logical vs arithmetic)

• Shift Operator (logical) : << >> .

• Shift Operator (arithmetic) : <<< >>> , used only for signed data type.

conditional assignment ( ? : )

• Ex: c = sel ? a : b ;
• Used in continuous assignment
• Same as if-else statement, e.g.

for loop outside always block using generate

• Duplicate same function.
• Useful when change the physical structure of module via parameters (See ICLAB Lab06 Note).

for loop inside always block

• Duplicate same function.

Q & A

Q : How to pass array structure between two Verilog module?
A : Not possible.

See How to pass array structure between two verilog modules for more detailed answer. It is not possible to do it with Verilog. Instead you should “flatten” the array and pass it as a simple vector.

Illegal way :

Legal way :

Q : How to make area smaller?
A1 : only create wire/reg with least bit length required.
A2 : use adders/multipliers/dividers as less as possible.

Pretty simple but useful ways to reduce area.

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