ICLAB Lab02 Note
Week 3
LAB Description
Topic of this week
- Sequential Circuits
- Finite State Machine
- Timing
- Synthesis and Design Compiler
Design
String Match Engine (SME)
Description
Given a string and a pattern, detect whether the pattern is contained in the string or not.
GitHub
What did I learn?
- Performance tradeoff between speed and area.
- Importance of good algorithms in a circuit design
- My own structural ways to write a Verilog code.
Design Flow
Verification (00_TESTBED)
- Pattern and Testbench
Pre-sim (01_RTL)
- Specify input/output relationship (Spec.)
- RTL code development
- Run RTL code functionality simulation/verification by Cadence Tool Ncverilog, irun nWave
Synthesis (02_SYN)
- Synthesis = Translation + Optimization + Mapping
- Run circuit synthesis by Synopsys Design Compiler
- Timing verification / Area check
Gate-sim (03_GATE)
- Physical Synthesis : Floorplan/Placement/Routing
- Run gate level simulation by Cadence innovus tool
Physical Design (05_APR)
- Physical Synthesis / Place / Route
- Physical Verification
Prototype, Build and Test
- System Integration ans Software Test
Lecture Note
Blocking vs Non-blocking
- Blocking assignment (Combinational block) : Evaluations and assignments are immediate and in order.
- Non-blocking assignment (Sequential block) : Evaluations and assignments are all at the same time without regard to orders or dependence upon each other.
Reset
Reset all signals to avoid unknown propagation.
- Synchronous Reset :
Pro. : Glitch filtering from reset combinational logic.
Con. : (1) Cannot reset without clock signal. (2) May need a pulse stretcher. (3) Larger area. - Asynchronous Reset :
Pro. : (1) Reset is independent of clock signal and immediate. (2) Less area.
Con. : Noisy reset line could cause unwanted reset.
Finite State Machin (FSM)
- Mealy machine : the outputs depend on the current state and inputs.
- Moore machine : the outputs depend on the current state only.
- FSM Coding Style :
Q : Passed 01_RTL but failed 03_GATE? Got unknown signals when gate simulation?
A : Check if there is any INPUT signals appeared in if(…) or case(…) and they may be unknown during some time. Make sure they are always 0 or 1 when entering if(…) or case(…).
Below are some hints from the TAs.
1. Registers are not reset
If so, the unreset signals will be unknown signals at first. If registers/wires get the unknown signals from unreset registers, they will be another unknown.
Reset all the registers properly, do NOT try to reduce area by not reset the registers.
2. Time is not enough
Passing 02_SYN timing analysis does not mean passing 03_GATE timing analysis.
Try increase the clock cycle of Gate-sim. If it can pass 03_GATE by this, it means that the cycle time for gate-level circuits are not enough. Try to shorten the paths and try synthesize again. But do not change 03_GATE cycle time for real, do it just for experiments.
3. Bad coding style
Good coding style helps to achieve the best compile times and synthesis results. Gate-level circuit behavior may not match that of the original RTL code because of bad coding style.
Reference : Verilog Coding Style
Example : The reason I passed 01_RTL but failed 03_GATE
My output signals were unknown values in 03_GATE even though I’d passed 01_RTL.
I wrote something like :
Because the input data would be 1'bX sometimes, it would cause flag to be 1'bX as well. It seems that once a register became unknown value, it would be unknown value all the way through out Gate-sim, making the rest of the circuit unknown as well.
I revised it as follow :
Q & A
Q : The results of some calculations do not match what I expected.
A : Check the bit-width, make sure it does not overflow.
Stupid mistakes.
Q : How to write always block with case statement and for loop?
A : Use generate.
Error message in 02_SYN :
Net ‘j[31]’, or a directly connected net, is driven by more than one source, and at least one source is a constant net.
What I did :
Revised :
Verilog Note
string
and first_match
are reserved word in verilog/system verilog.
I am so good at picking names…
上一篇:ICLAB Lab01 Note
下一篇:ICLAB Lab03 Note