ICLAB Lab07 Note

Week 9

LAB Description

Topic of this week

1. Timing Analysis Considering Clock Latency
2. Multicycle Path Specification
3. Clock Domain Crossing (CDC)

Design

Polish Notation (PN)

Description

Calculate the answers of arithmetic expressions in the forms of prefix or postfix expression with 3 clock domains.

GitHub

2021_Spring_NCTU_ICLAB/Lab07/

What did I learn?

1. What are infix/prefix/postfix expression.
2. How to realize CDC solution : Double Flip-Flop Synchronizer.

Lecture Note

Static Timing Analysis, STA

What is Static Timing Analysis (STA)?

• Verify the timing based on statistic method without simulation.
• A complete and exhaustive way because it analyzes every timing paths in design according to constraints.
• Much faster than DTA because it is not necessary to simulate the logical operation of the circuit.
• Only check the timing, not the functionality.
• Each timing path consists of :
  1. Startpoint : Either an input port or a register clock pin.
  2. Combinational logic network : Elements that have no memory or internal state.
  3. Endpoint : Either a register data input pin or an output port.

https://www.synopsys.com/glossary/what-is-static-timing-analysis.html

• Maximum Delay : Use the longest path.
• Minimum Delay : Use the shortest path.
• Exceptions that can be specified during STA :
  1. False path : A path that is never sensitized due to the logic configuration, expected data sequence, or operating mode.
  2. Multicycle path : A path designed to take more than one clock cycle from launch to capture.
  3. Minimum or maximum delay path : A path that must meet a delay constraint that you explicitly specify as a time value.

Dynamic Timing Analysis, DTA

• Verify with simulation using input test vectors.
• Quality(Coverage) increases with the increase of input test vectors.

Clock Latency

• Clock Source Latency : From the clock source to the clock definition point (either on-chip or off-chip).
• Clock Network Latency : From the clock definition point to the clock pin of a flip-flop.

Clock Uncertainty (Clock Skew)

• A constraint to model various factors that influence the effective clock period.
• Leave some timing margin for APR routing imperfection.
• Inter-Clock Uncertainty : Setup/Hold uncertainty applies to all paths from start point of clock domain1 to the endpoint of clock domain2.

Clock Domain Crossing (CDC)

跟老李一起学习芯片设计 — CDC的那些事（1）
你真的懂2-flop synchronizer吗 — CDC的那些事（2）
常见数电面试题Pulse Synchronizer — CDC的那些事（3）
多bit信号跨时钟域怎么办？ — CDC的那些事（4）
面试必杀技：异步FIFO（上） — CDC的那些事（5）
面试必杀技：异步FIFO（下） — CDC的那些事（6）
干货大放送之CDC工程经验总结 — CDC的那些事（7）完结篇

• Metastability : The unstable state due to non-ideal data transition. Thus, make sure there is no data transition during setup/hold timing check.
• Solutions for CDC designs :
  1. Double Flop (2-FF) Synchronizer
  2. XOR Double Flop (2-FF) Synchronizer
  3. Handshake Synchronizer
  4. Dual Clock FIFO Synchronizer

Double Flop (2-FF) Synchronizer

Double Flip-Flop (2-FF) Synchronizers

Reference Book

1. Principles of VLSI RTL Design: A Practical Guide
2. Static Timing Analysis for Nanometer Designs: A Practical Approach

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