ICLAB Lab06 Note

Week 7

LAB Description

Topic of this week

1. Design Compiler Introduction
2. Basic Synthesis Flow
3. Generate & For Loop

Design

CheckSum (CS)

Description

First design a checksum soft IP which can calculate the checksum of the input data. Second design a processor which contains 2 checksum IPs.

GitHub

2021_Spring_NCTU_ICLAB/Lab06/

What did I learn?

1. How to create soft IP.
2. Basic of .tcl (Tool Command Language) files.
3. Usage of generate with parameters.
4. How to pass/change parameters through commands without modifying TESTBED.v in 01_RTL.

Basic Synthesis Flow

1. Develop HDL Files

• Write Verilog Code.

2. Specify Libraries

• Synthetic / Link / Target Library.
• See Different Libraries in Synopsys DC setup for more information.

3. Read Design

• Method 1 : read_file .

// written in syn.tcl
read_verilog {$DESIGN\.v}
read_verilog YOUR_SOFT_IP.v
current_design $DESIGN
link > Report/$DESIGN\.link

• Method 2 : analyze and elaborate .

// written in syn.tcl
analyze -f verilog $DESIGN\.v
analyze -f verilog YOUR_SOFT_IP.v
elaborate $DESIGN 
current_design $DESIGN

4. Define Design Environment

• In which the design is expected to operate.
• Specify Operating Conditions, Wire Load Models, and System Interface characteristics.
• Operating Conditions : Process, Voltage, Temperature (PVT).
• Wire Load Models : Used to estimate capacitance, resistance and area overhead due to interconnection.
  There are 3 types of Wire Load Models : Top / Enclosed / Segmented.
• System Interface : To model the design’s interaction with the external system.
  1. Drive characteristics for input ports.
  2. Fanout loads on output ports.
  3. Loads on input and output ports.

5. Set Design Constraints

• Design Rule Constraints (DRC)
• Design Optimization constraints (speed, area)

6. Select Compile Strategy

• Top-down Compile : Top-level design and all its subdesigns are compiled together.
• Bottom-up Compile : Individual subdesigns are compiled separately, starting from the bottom of the hierarchy.
• Mixed Compile : Top-down or Bottom-up strategy, whichever is most appropriate, is applied to the individual subdesigns.

7. Optimize the design

• uniquify (default) : Duplicate and rename the multiple referenced design so that each instance references a unique design. May be useless with compile_ultra.
• set_dont_touch : Prevent the specified objects from being modified or replaced during optimization.
• ungroup : Ungroup one or more designs before optimization.
• compile : Default sythesis algorithm.
• compile_ultra : Advanced sythesis algorithm.

8. Analyze and Resolve Design Problems

• report_area / report_area > Report/$DESIGN\.area
• report_timing / report_timing > Report/$DESIGN\.timing

9. Save The Design Database

• Change naming rule script : Execute the script after compile your design.

set bus_inference_style "%s\[%d\]"
set bus_naming_style "%s\[%d\]"
set hdlout_internal_busses true
change_names -hierarchy -rule verilog
define_name_rules name_rule -allowed "a-z A-Z 0-9 _" -max_length 255 -type cell
define_name_rules name_rule -allowed "a-z A-Z 0-9 _[]" -max_length 255 -type net
define_name_rules name_rule -map {{"\\*cell\\*" "cell"}}
change_names -hierarchy -rules name_rule

• Save a gate level Verilog file.

// syntax
write –f verilog –o file_name.v –hierarchy
// example
write -format verilog -output Netlist/$DESIGN\_SYN.v -hierarchy

• Save a Standard Delay Format (SDF) file for post synthesis timing simulation.

// syntax
write_sdf -version sdf_version file_name
// example
write_sdf -version 3.0 -context verilog -load_delay cell Netlist/$DESIGN\_SYN.sdf -significant_digits 6

Different Libraries in Synopsys DC setup

DC stands for Design Compiler. See Design Compiler入门 for more information.

Synthetic Library

This refers to DesignWare Library. Used when a design uses some DesignWare IPs for optimization purposes.

dw_foundation.sldbis the name of the DesignWare Library that Synopsys provides, includes efficient implementations for basic arithmetic logics, e.g. adders, comparators, multipliers, …

Link Library

Specifies a list of libraries of cells used solely for reference.

In a design, inevitably we use some third party IPs, e.g. PLL, RAM, PAD. Using Link Library let DC know that it does not need to synthesize these parts but it can get information from the .lib files in Link Library.

Target Library

Specifies the technology library whose standard cells the designers want DC to infer and finally map to.

During synthesis, DC selects gates from target library, and calculates the timing of the circuit based on the timing data of the .lib files provided by ASIC Vendor(UMC, TSMC, …).

Note

The target library name should also be included in the Link Library.

DC will not be able to link to the mapped cells in the netlist, if the target library name is not included in the link library list.

Reference :

1. DC综合各种lib library的解释
2. link library 、target library、symbol library、synthetic library对照分析-基础小知识（九）
3. What’s the difference between the target library to the link

Q & A

Q : How to pass/change parameters through commands without modifying TESTBED.v in 01_RTL.
A : With option "-defparam” .

// normal command
irun TESTBED.v -define RTL -debug -notimingchecks | tee out.log
// with option "-defparam"
irun TESTBED.v -define RTL -debug -notimingchecks -defparam TESTBED.PARAM_1=9487 -defparam TESTBED.PARAM_2=1314521 | tee out.log

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