ICLAB Lab11 Note

Week 14

LAB Description

Topic of this week

1. What is APR
2. SOP of APR

Design

Matrix Computation (MC)

Description

Run the APR flow and post-simulation for the finished design MC.

GitHub

2021_Spring_NCTU_ICLAB/Lab11/

What did I learn?

1. Review Cell-based Design Flow
2. How to do APR with Cadence Innovus.

Lecture Note

Cell-based Design Flow

1. Specification Development, System Models.
2. RTL Code Development, Function Verification.
3. Synthesis, Timing Verification.
4. Physical Synthesis & Place & Route, Physical Verification.
5. Prototype, Build and Test.

Problems due to Wire Resistance and Capacitance

• Timing Closure — PKS(Cadence), Phisical Compiler(Synopsys)
• SI Closure — NanoRoute(Cadence), CeltIC(Cadence)
• Power Closure — Voltage Storm(Cadence)

APR Flow — Innovus Design Flow

Data Preparation

• Library Files
  1. LIB Library : Timing information of cell delay.
  2. LEF Library : Process and cell information.
  3. RC Extraction : For further power analysis, simulation, etc.
  4. CeltIC Library : cdB model.
  5. GDSII : Layout information.
• Design Netlist
  1. DESIGN_SYN.v
  2. CHIP_SHELL.v : Contain IO, IO power, core power.
  3. cat CHIP_SHELL.v DESIGN_SYN.v > CHIP_SYN.v
• I/O Files
  1. CHIP.io : IO pad location file.

IO Pad Assignments Order

Example of CHIP.io file.

Import

• Netlist : CHIP_SYN.v.
• Technology / Physical Liraries : LEF → Standard Cell LEF → Block LEF.
• Floorplan : CHIP.io.
• Multi-Mode Multi-Corner (MMMC) Timing Analysis & Optimization.
  Multi-Mode : Run & Test.
  Multi-Corner : Slow & Fast.

Floorplan

• Develop early physical layout and gain early visibility into implementation issues.
• Core Margins : Leave space for Power/Ground (P/G) ring.
• Pad-limited Design : (Pad Width) > (Core Width + Core Margin)
• Core-limited Design : (Pad Width) < (Core Width + Core Margin)
• Pad Filler : Provide power to pad, necessary for core limited design.

Powerplan

• Metal Migration (Electro-migration) : Caused by high currents.
  Prevention : Sizing power supply lines.
  Experience : Make current density of power ring < 1mA/um
• IR Drop : Due to power-ground resistive network.
  Leads to :
  1. Performance (low speed)
  2. Functionality Problem (setup/hold violation)
  3. Unreliable Operation (less noise margin)
  4. Power Consumption (leakage power)
  5. Latch up
  Prevention : Add stripes on power lines.

1. Connect & Define Global Nets
2. Core Power Ring : w/wo interleaving & w/wo wire group.
3. Core Power Pin : Connect from core power pads to power rings.
4. Stripe : Add one stripe set per 100 um.
5. Block Ring : for Hard Macro.
6. Connect Standard Cell Power Line.
7. Add Pad Filler : From wider fillers to narrower ones.

Placement

• Place standard cells.

Clock Tree Synthesis, CTS

• Goals :
  1. Create clock tree spec file.
  2. Build a buffer distribution network.
  3. Route clock nets using CTS-NanoRoute.

Routing

• Signal Integrity, SI
• Antenna Effect

Add Filler Cells

• Fill all the gaps between standard cell instances.

LVS / DRC / DRV

• LVS : Layout Verse Schematic.
• DRC : Design Rule Check.
• DRV : Design Rule Violation.

Output Files

• CHIP.v : Netlist file for post-layout gate-level simulation.
• CHIP.sdf : Design timing file for post-layout gate-level siulation.
• CHIP.def : Design exchange format relevant to physical layout.
• CHIP.gds : GDSII stream file for Calibre-DRC.

Reference

IO PAD的選擇 — 皓宇的筆記

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