High-Speed Signal Integrity Tips
This is Part 2
In part 1, we covered several causes of signal integrity issues. In this section, we’ll discuss recommendations to help mitigate.
After designing the schematic, the next steps are layout and verification using simulation. Adding signal integrity analysis as a critical part of the design process helps to identify and prevent future problems.
The post-layout analysis will thoroughly check on the finished board and confirm that the physical layout does not introduce issues such as impedance mismatches, and crosstalk between adjacent traces.
However, using the best practices and experience can help address most of the signal integrity issues. Paying attention to the SI throughout the design cycle allows the designer to identify and address the problems early before production.
Routing considerations
Routing becomes challenging with complex, multifunctional, and highly optimized PCBs. Simple boards have fewer problems, and a single trace width that handles all voltages including the maximum current can run throughout the board without issues.
The best option is to route the high-speed signals over solid ground reference planes. Unless it is absolutely necessary, avoid crossing a plane void or split in the reference plane, otherwise the high-frequency return current will flow around the void or split. This may cause issues such as excessive radiated emissions, delays in signal propagation, signal degradation, etc.
Use short and matched trace lengths
It is recommended to keep the trace lengths for differential signal pairs as short as possible. In addition, try and match the lengths as close as possible so that they almost start and end together. When it is impossible to match the lengths, add a serpentine routing at the mismatched end so that the overall length of both traces is almost equal.
Avoid right angle bends in signal traces
Right angles have the potential to cause radiations and reflections due to increased capacitance and characteristic impedance changes at the corners. Instead of right angle bends, route the signal traces with at least two 45° bends. If possible use a round bend since this is the best in reducing the impedance changes.
Separate signals to reduce interference
The best practice is to place signals separately based on type and speed. This means separating the digital, analog, high speed, or low-speed signals. Proximity between incompatible signals will cause significant interference and degradation.
Finally, segregate circuits and components according to their functions. Have a separate section for the high-speed circuits, low-speed circuits, power supply section, digital circuits, analog circuits, etc.
Use proper high-speed differential signal spacing
Differential pairs provide a path for the transmission as well as the return current. These traces are usually parallel and only separated by a very small distance. A bad layout may lead to a wide range of problems.
To avoid signal integrity issues, always route differential pair traces parallel to one another and ensure that they are symmetrical. In addition, use a constant trace width to prevent impedance mismatches and avoid placing the test points or probes on the high-speed differential signal path.
Minimize use of Vias
Vias are essential in circuit design, however, they have the potential to introduce additional trace length, capacitance, inductance, and reflections. The designer must be careful when deciding the placement and geometry. In particular, avoid them in differential signal traces. A via will introduce a section which alters the geometry of a net. This can appear as a discontinuity which is capacitive, inductive, or both and results in reflections and degradation of the signal.
Take care of the return path
The return current at high frequencies will usually take the lowest impedance path which is directly beside the signal. Ideally, this should be the ground path. Unfortunately, a slot or break along the ground plane causes the return current to look for an alternative route and possibly cause a loop area.
The amount of radiation and EMI increases as the loop area gets larger. To overcome such issues, avoid using the slots in the ground reference plane. If unavoidable, place a zero ohm resistor across the slot.
Conclusion
Generally, the signal integrity issues arise at high speeds and the designers must pay attention to the board layout, impedance matching, component placement, and other factors that impact on the quality of the signal.
In addition to a proper layout and routing of traces, the designer must minimize the effects of capacitive and inductive coupling. Best practices for limiting the stray capacitance include avoiding discontinuities, proper impedance matching, and using low-loss PCB dielectric materials. Using the power and ground planes help to minimize the EMI, inductive coupling, and noise.
Finally, producing a circuit with good signal integrity should be the ultimate goal for everyone since it benefits both the manufacturer and the consumer. The manufacturer is able to provide a reliable product in good time and budget, while the consumer gets a reliable service.
