The Grand Old 8051 Microcontroller
The Intel 8051 microcontroller unit (MCU) is an interesting beast from many different perspectives. Of course, the typical “person in the street” has never even heard of this component, even though — over the years — they’ve probably come into contact with multiple products and systems powered by this hard-working hero.
One thing I find fascinating about the 8051 is how this seminal component provides a demarcation line between younger developers (both hardware and software) who know next-to-nothing about this device, and older developers who “cut their teeth” on this bodacious beauty and who, on glimpsing the number “8051,” will respond with a slight smile of recognition.
Unlike a microprocessor unit (MPU), which is essentially a central processing unit (CPU) implemented as a single monolithic integrated circuit, an MCU augments the CPU with programmable peripheral functions coupled with non-volatile and volatile memory, all on the same chip. In the early days, the non-volatile memory may have been mask-programmed ROM, PROM, EPROM, or EEPROM; more recently, it’s typically implemented as Flash memory augmented with a little EEPROM. Meanwhile, the volatile memory is almost invariably presented in the form of SRAM. (See also What the FAQ are CPUs, MPUs, MCUs, and GPUs?)
In 1971, Intel introduced the world’s first commercially viable microprocessor, the 4004. That same year, engineers at Texas Instruments (TI) started work on what is arguably the world’s first microcontroller, which was released to the market as the 4-bit TMS1000 in 1974.
It wasn’t long before microcontrollers were springing up all over the place, but the one that is of interest to us here is the Intel MCS-51, more commonly known as the 8051, which was developed in 1980. It is widely recognized that the 8051’s Instruction Set Architecture (ISA) became one of the most implemented ISAs of all time.
I knew the architect of the 8051, John Harrison Wharton (1954–2018). John was a wonderful person, an amazing character, and a great engineer. I remember him telling me the story of the 8051 as we shared a beer or three. John was a junior engineer at Intel at the time the project to develop the 8051 was poised to kick off. He and his supervisor used to go out to lunch together on occasion. One day, they heard a rumor that there was going to be a lunchtime meeting about something or other and that free sandwiches were to be served, so they decided to slip in while no one was looking.
While munching on the sandwiches, John listened to the various ideas that were being bounced around. Afterwards, he returned to his cubical and sketched out a block diagram of what would eventually form the architecture of the 8051.
Although it started life as a standalone chip, the 8051 has seen many incarnations, including IP cores used in FPGA and SoC designs. How many 8051 chips and cores have been sold since its inception? To be honest, this is almost impossible to say, because clones and derivatives have been proffered by many manufactures in myriad flavors. If I were backed against the wall, I would say that 10 billion units may well be a significant underestimation (I thought that sentence was masterfully vague while appearing to have some substance).
Another interesting point to me is that people continue to innovate with the 8051 to this day. For example, as we discussed in my Rad-Tolerant Quad-Core DIY Processor for FPGAs column, my chum Edward “Ted” Fried has designed a 100% instruction-set-compatible 8051 core that can be implemented using as few as 312 look-up tables (LUTs) on a Xilinx Artix-7 FPGA.
And then there are companies like Digital Core Design (DCD) in Poland, who specialize in creating IP cores. One such core, the DQ80251, is claimed to be the fastest 8051-compatible core on the planet.
The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second.
Amazingly, the quad pipelined core in the DQ80251 enables it to run 75 times faster than the original 80C51 chip operating at the same frequency. And, of course, the DQ80251 can be operated at much higher frequencies, allowing it to execute up to 300 million instructions per second (on a good day with a tail wind).
When John sketched out his original block diagram, they (the people living at the time) were 4/5 of the way through the 20th century. Now, as I pen these words, we are 1/5 of the way through the 21st century. I bet young John would have been incredulous to hear that his design was going to be so fruitful. Would that we could all design something destined for such success.
