What the FAQ Are Programmable Logic Devices?
Like a lot of subjects, the topic of programmable logic devices (PLDs) is one many people think they understand… until they try to explain it to someone else. The thing is that today’s programmable logic devices — especially field-programmable gate arrays (FPGAs) — are making their presence felt in a wide range of applications, from wearables to space probes, so it’s worth our time to wrap our brains around these technologies.
Configuration Cells
As a starting point, programmable devices have configuration cells that are used to define their logical functions and internal connections. A variety of different semiconductor technologies can be used to create these cells, each having their own advantages and disadvantages.
Fusible-link cells are a bit like tiny fuses — by applying a higher-than usual voltage, it’s possible to “blow” these links. Antifuse cells work the other way — by applying a higher-than usual voltage, it’s possible to “grow” these links. In both cases, these are referred to as being one-time-programmable (OTP) because once you’ve programmed them there’s no going back.
EPROM (electrically programmable read-only memory) cells can be programmed electrically, but the only way to “clear” or erase” them is to expose them to ultraviolet (UV) light (devices based on this technology have small quartz “windows” in the top to admit the UIV).
EEPROM (electrically erasable programmable read only memory) cells can be both programmed and erased by applying higher-than usual voltage. Flash memory is a later evolution that combines the best features from EPROM and EEPROM.
All of the aforementioned technologies are classed as NVM (non-volatile memory) because they retain (remember) their contents when power is applied to the system. Some devices employ SRAM-based configuration cells. These are volatile (they forget their contents when power is removed from the system), so they have to be loaded from an external memory or processor when the system is powered-up.
EEPROM, Flash, and SRAM-based cells are classed as MTP (multi-time programmable) because they can be erased and reprogrammed multiple times. Programmable devices based on EPROM cells may be OTP or MTP depending on whether provision is made to clear them using UV light.
Programmable Logic Devices
PLDs were introduced to the market circa 1970. The first PLDs were programmable read-only memories (PROMs). These were followed by programmable logic arrays (PLAs), programmable array logic (PAL) devices, and generic array logic (GAL) devices. At the tail-end of the 1970s and the beginning of the 1980s, more sophisticated devices with higher capacities started to appear on the scene. In order to distinguish these little rascals from their less-sophisticated predecessors, these new devices were called complex PLDs (CPLDs). Perhaps not surprisingly, it subsequently became common to group the earlier devices together as simple PLDs (SPLDs).
The first FPGAs were discussed in 1984 and introduced to the market in 1985. The early incarnations of these devices were extremely simple by today’s standards. Over time, however, high-end versions appeared that can contain the equivalent of tens of millions of equivalent logic gates.
The latest and greatest devices, known as SoC FPGAs, contain a combination of programmable fabric, hard processor cores, and hard peripheral functions (see also MCU Designer’s Intro to FPGA Hardware and MCU Designer’s Intro to FPGA Software).
SPLDs typically employ antifuse, fusible-link, EPROM, or EEPROM configuration cells. CPLDs typically employ EPROM, EEPROM, Flash, or SRAM-based configuration cells. FPGAs typically employ antifuse, Flash, or SRAM-based configuration cells.
At least one vendor, Lattice Semiconductor, employs hybrid configuration technologies. In the case of its iCE FPGAs, the configuration is stored in antifuse-based OTP NVM. In the case of its MachXO FPGAs, the configuration is stored in Flash-based MTP NVM.
When these devices are powered-up, the configuration is copied out of the NVM into SRAM-based configuration cells in a massively parallel fashion. (In both cases, during development, the design can be tested by directly loading the SRAM-based configuration cells from the outside world.)
Conclusion
The discussions above offer only a high-level introduction to a rich and multifaceted topic. If you are interested in learning more, all of these technologies are discussed in excruciating detail in my book, Bebop to the Boolean Boogie (An Unconventional Guide to Electronics).
