VERILOG NOVICE TO WIZARD

Verilog Events and Delay

Contents

• Delays
• Events

Delays

Typical uses of delay

   #20;  // delay 20 time units
   #10 <statement> // the statement execution takes 10 time…

Tasks and Functions in Verilog

Introduction

Tasks and functions are introduced in the verilog, to provide the ability to execute common procedures from different places in a description. This helps the designer to break up large behavioral designs into smaller pieces. The…

ASSIGNMENTS IN VERILOG

There are two types of assignments in veriolg

1. procedural Assignment
2. Continuous Assignment

Procedural Assignment

Verilog Constructs

Verilog HDL has a rich collection of control statements which can used in the procedural sections of code, i. e., within an initial or always block. Most of them will be familiar to the programmer of traditional programming languages like C. The main difference is instead of C’s { } brackets…

OPERATORS IN VERILOG

1. Arithmetic

There are five arithmetic operators in Verilog.

Instantiation And Port Declaration

Instantiation

An instantiation defines a sub-component of a module.

Syntax:

module_name [ strength ] [ #( token_expression ) ] instance_name [ instance_range ] ( port_connection…

Verilog Data Types

Verilog has four values any signal can take:

0 represents a logic zero, or a false condition
1 represents a logic one, or a true condition
x represents an unknown logic value (can be zero or one)
z represents a high-impedance state

Abstraction Levels in Verilog

Verilog language has the capability of designing a module in several coding styles. Depending on the needs…

Verilog Design Structures

Verilog Design Structures

A structure may be the entire file or there may be more than
one structure in a file. No less than a structure may be
in a file.

Verilog Design Structures