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VLSI Cell Placement Techniques
The problem of VLSI cell placement is known to be NP-complete. There is a large number of heuristic algorithms for efficiently arranging logic cells on a VLSI chip. The aim of this publication is to provide a thorough overview of various cell placement techniques.
Note from the editor

VLSI cell placement has been around for over a couple of decades in the industry and the solutions to aid this are aplenty. A wide range of efficient algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The Purpose of this blog is to do a comparative study and analyze all the options available. We have tried to cover 5 Algorithms i.e. (: simulated annealing, force-directed placement, rein-cut placement, placement by numerical optimization, and evolution-based placement).The first two set of algorithms owe their origin to physical laws, the third and fourth are analytical techniques, and the fifth class of algorithms is derived from biological phenomena.

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AAYUSH MEHTA
Just a GEM of the this world and still not valued. PS. (GEM = General Engineer Male)