ICLAB Lab03 Note

Week 4

LAB Description

Topic of this week

1. Introduction to Verification
2. Pattern
3. Testbench
4. Environment

Design

Sudoku (SD)

Description

Solve a 9x9 Sudoku grid with 15 blank positions.

GitHub

2021_Spring_NCTU_ICLAB/Lab03/

What did I learn?

1. How to write Pattern.v to verify RTL codes.
2. Stack Overflow : How to create a Sudoku puzzle in Python.
3. The importance of high-level language, such as python, in the process of designing a Verilog.

Lecture Note

TESTBED.v

• Encapsulate DESIGN.v and PATTERN.v to be a top verification file.
• Key elements :
  1. Timescale : `timescale <time_unit>/<time_precision>
  2. Dump Waveform : fsdbDumpfile(fsdb_name[,limit_size])
fsdbDumpvars([depth, instance][,"option"]) sdf_annotate("sdf_file"[,instance][,config_file][,log_file][,mtm_spec][,scale_factors][,scale_type])
  3. Port Connections
• Example :

DESIGN.v

• Design under test (DUT)

PATTERN.v

• Generate stimulus
• File I/O
• Procedural Blocks
• Display Information
• Control Flow
• Task and Function

Waveform file formats

• Value Change Dump (.VCD) : Included in Verilog HDL IEEE Standard
• Wave Log FIle (.wlf) : Mentor Graphics — Modelsim
• SHM (.shm) : Cadence — NC Verilog / Simvision
• VPD (.vpd) : Synopsys — VCS
• Fast Signal DataBase (.fsdb) : Spring Soft (Merged with Synopsys) — Debussy/Veridi

Q & A

Q : 01_RTL stucks.
A : Command some codes per time to find out which lines cause the problem.

It is not normal when stucking at 01_RTL simulation for over 30 minutes.

Where I stucked in 01_RTL.

What I did :

It logically makes sense but it does not work in 01_RTL. After commanding the code, I found that it was STATE_2/STATE_3 causing the problems.

Revised :

Q : 02_SYN stucks.
A : Command some codes per time to find out which lines cause the problem.

It is not normal when stucking at 02_SYN simulation for over 30 minutes.

Where I stucked in 02_SYN.

What I did :

Revised :

Change current_state into next_state or vice versa can make 02_SYN run successfully. It seemed logically right but it did not work, I didn’t know the reasons behind.

Note

Use top command in linux to check the usage of the server. Choose a free server to speedup the synthesis process.

“top” command is pretty useful.

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