ICLAB Lab04 Note

Week 5

LAB Description

Topic of this week

1. Timing
2. Designware

Design

Artificial Neural Network (NN)

Description

Build an ANN accelerator with three layers, using back-propagation algorithm to solve a regression problem.

GitHub

2021_Spring_NCTU_ICLAB/Lab04/

What did I learn?

1. How to use Instantiate IP
2. Back-propagation algorithm in ML.

Lecture Note

Setup Time Criterion

From Q_1 to D_2

• ( Tcycle + Tskew ) > ( Tpcq + Tpd + Tsetup )
• Data required time = Tcycle + Tskew — Tsetup
• Data arrival time = Tpcq + Tpd
• Slack = Data required time — Data arrival time ≥ 0

Data required time : Q_1 到 D_2 要在多少時間內完成計算+傳遞。
Data arrival time : Q_1 到 D_2 最快多少時間完成計算+傳遞。

When Setup violation occurs → too many tasks in one cycle → Increase clock period or apply pipeline.

Hold Time Criterion

From D_2 to Q_2

• ( Tccq + Tcd ) > ( Thold + Tskew )
• Data required time = Tskew + Thold
• Data arrival time = Tccq + Tcd
• Slack = Data arrival time — Data required time ≥ 0

Data required time : 前一組 D_2 使 Q_2 產生變化所需要維持的時間。
Data arrival time : 後一組 Ｄ_1 使D_2 產生變化（汙染）所需要的時間。

When Hold violation occurs → insufficient delay → Add delays to the violated path, such as buffers/inverters/MUXes.

IP (Intellectual Property) Core

What is an IP (Intellectual Property) core in Semiconductors?

• Hard IP :
  1. Hardare, in GDSII format.
  2. Cannot touch the interior (APR).
  3. High performance but technology depedent.
  4. Generally for Analog and Mixed signal logic designs.
• Firm IP :
  1. Netlist resource (need no synthesizing).
  2. Performance optimization under a specific fabrication technology.
  3. Less used, also falls under Soft IP cores.
• Soft IP :
  1. Synthesizable RTL design models, protable and editable.
  2. Developed in HDL code, e.g.SystemVerilog/Verilog/VHDL.
  3. Unpredictable in terms of performance ,timing, area, or power.
  4. Generally for Digital Logic cores.

Synopsys DesignWare Building Block IPs

• A collection of reusable IP blocks.
• Increases design reusability and productivity.
• Pre-verified for quality and better quality of results (QOR) in synthesis.
• Parameterized in size and functionality for some IPs.
• Technology independent.

Operator Inference

• HDL Standard synthetic operator : + - * == < <= > >= if-else .
• / requires DesignWare license.
• Convenient, but sometimes it is inefficient when synthesizing.
• Supply default function only.

Instantiate IP

• To instantiate a synthetic module manually and explicitly.
• Use Synopsys design compiler shell script.
• Supply different architecture for implementation.
• Applying pre-compiling sub-blocks speeds up the synthesis for large design.

How to use Instantiate IP

1st step

Check SYNOPSYS online document.

2nd Step

Specify the behavioral simulation models with absolute/relative paths at the top of the Verilog code. e.g.

3rd step

Create submodules for these IPs and call them in the top module. e.g.

You can skip this steps and call these IPs in the main module. e.g.

4th step

Based on the optimization you want(area, timing, …), set the implementation type of IP. e.g.

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