NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators

Large-scale neural networks are deployed on the processors having multi-core structure and organized via network on chip for process the heavy neurons. These Neural…

OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks

In this article, the authors propose a domain-specific FPGA overlay processor, named OPU to accelerate CNN networks. It offers software-like programmability for CNN end users, as CNN algorithms are…

Back-Propagation Learning Algorithms for Analog VLSI Implementation

There are many VLSI implementations of Neural Networks in both digital and analog mode. The selection strongly depends on the application. Analog VLSI NNs are most suited for biological models and to exploit…

Sparse Systolic Tensor Array for Efficient CNN Hardware Acceleration

High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture

Deployment of CNNs…

Network-on-Chip Architectures for Neural Networks.

In the study of Network-on-Chip Architectures for Neural Networks, Authors perform an analytical evaluation and comparison of different configurable interconnect architectures i.e. mesh NoC (Network on Chip), tree, shared bus, and…

AN ANALOG IMPLEMENTATION OF THE BOLTZMANN MACHINE WITH PROGRAMMABLE LEARNING ALGORITHMS

A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection

HARDWARE ACCELERATORS FOR MACHINE LEARNING.

In most of the Machine learning area deep neural network plays a very important…

Optimizing FPGA-based Accelerator Design For Deep Convolutional Neural Networks

Loop unrolling can be utilized to improve the utilization of vast computation resources in FPGA devices. Unrolling along various loop dimensions will create different implementation variants…