VLSI for Neural Networks and Artificial Intelligence

AN ANALOG CMOS IMPLEMENTATION OF A KOHONEN NETWORK WITH LEARNING CAPABILITY

High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture

Deployment of CNNs…

A VLSI DESIGN OF THE MINIMUM ENTROPY NEURON

In pattern recognition, the maximization of the transformation from the input to the…

HARDWARE ACCELERATORS FOR MACHINE LEARNING.

In most of the Machine learning area deep neural network plays a very important…

AN ANALOG IMPLEMENTATION OF THE BOLTZMANN MACHINE WITH PROGRAMMABLE LEARNING ALGORITHMS

A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection

A FPGA-based Hardware Accelerator for Multiple Convolutional Neural Networks.

In Field of Image processing and computer vision Convolution Neural Network plays a very important role in these recent days. A FPGA-based CNN accelerator are for used for multiple networks and its…

Optimizing FPGA-based Accelerator Design For Deep Convolutional Neural Networks

Loop unrolling can be utilized to improve the utilization of vast computation resources in FPGA devices. Unrolling along various loop dimensions will create different implementation variants…

OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks

In this article, the authors propose a domain-specific FPGA overlay processor, named OPU to accelerate CNN networks. It offers software-like programmability for CNN end users, as CNN algorithms are…